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Clock generation

Other Parts Discussed in Thread: CDCEL913

Hi,

I Need a clock (50% duty cycle) to drive a ADC (ADS131E6). The frequency should be 1.92Mhz, 1.28Mhz or 768khz. I found a 7.68Mhz Quarz and with div by 4, 6 or 10 ist done.

Can anybody recommend a divider or is there another way to solve this Timing Problem?

Thanks for helping.

With best regards

Gerhard

  • Hi Gerhard,

    CDCEL913 in PLL bypass mode may be an option. Although the crystal reference spec is 8 MHz, I believe 7.68 MHz should work fine.

    Regards

    Arvind Sridhar

     

  • Hi Arvind,

    thanks, but ...

    There is a Crystal with 15.36Mhz available, so it will be within the specs.

    I Need the frequencies 1.92Mhz and 1.28Mhz. unfortunately 15.36 / 1.28 = 12, so no Chance to get this with a binary divider. There is no documentation about the PLL, maybe I can first multiply the frequency to have a binary Divisor later on. I start calculating, but can't find a solution. The PLL should Need a fractional Multiplier.

    Whats about generating some programmable frequency with a timer of my Controller? I will run at 100Mhz, maybe I can find a solution, but whats about Phase jitter at the end, cause this clock will be not as clean as a Signal from a Crystal. With this idea I can Change the base frequency (like changing the Crystal) and use binary Division to get the result.

    But you were right, Phase jitter of 50ps is excellent.

    Any idea to solve that?

    With best regards

    Gerhard

  • Hi Arvind,

    never read technical documents after midnight ....

    Ok, now I have found the Formular to calculate the Output frequency.

    And I found out some interesting Feature. There is a Vcntrl which is used to pull the frequency. My System contains a GPS Receiver from which I get a very precise 1Hz clock and my Controller has a counter-timer unit which can act as a frequency Counter. Now I can feed the Output of the clock gen and the 1Hz GPS clock herin and use a DAC of my Controller (or PWM and filter) to fine tune the ADC sampling rate down to a quasi ideal value. THANKS.

    With best regards

    Gerhard