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LMK04816 lock time

Ed Gao
Prodigy 20 points
Other Parts Discussed in Thread: LMK04816, LMX2581

As we knew, the lock time was dependent on the both phase error window size and PLL_DLD_CNT. for example, if we want to set the frequence error 13.75 ppm, we can choose the PLLx_WND_SIZE = 5.5 ns, and PLLX_DLD_CNT = 1024. in another way, we can choose the PLLx_WND_SIZE = 10 ns, and PLLX_DLD_CNT = 1862. In my understanding, the PLLX_WND_SIZE 5.5 ns was stricter than PLLx_WND_SIZE = 10 ns. Besides that, I found some description about the PLLx_WND_SIZE selection, it should be dependent on the PFD. but it was NOT documented in the LMK04816 data sheet any longer. could you please advise how to select the PLLx_WND_SIZE?

Looking forward to your help, and thanks in advance.

 

Regards

Ed

  • 0
    TI__Mastermind 32575 points
    The info you're looking for is documented in Section 9.6 for the LMK04816 datasheet.
    www.ti.com/.../lmk04816.pdf

    I'd like to clarify that changes the programmable Digital Lock Detector (DLD) circuit is not changing the actual PLL lock time. Rather, it is changing the Digital Lock Detector's frequency accuracy threshold before indicating LOCK. The actual lock time is a function of the PLL's loop bandwidth, phase margin, and PLL frequency settling to within the required tolerance deemed acceptable by the system requirements.

    Regards,
    Alan
  • 0 in reply to Alan O
    Prodigy 20 points

    Hi, Alan

      It's true that we did NOT change the actual PLL lock time. but it was dependent on the loop bandwidth, phase margin, and PLL frequency setting to within the required tolerance. Based on the equation 3), frequency accurance was depdent on the both PLLx_WND_SIZE, PLLx_DLD_CNT and fPDX. for example, if we want to archieve the 13.75 ppm, first, we can set the PLLx_WND_SIZE = 5.5 ns, PLLx_DLD_CNT= 1024, and fPDX= 1.28 MHz. second, we can set the PLLX_WND_SIZE = 10 ns, PLLx_DLD_CNT = 1862, and fPDX = 1.28 MHz. Let's suppose all the other factor keep same configuration, such as loop bandwidth, phase margin, etc. But as we know, the two solution lock time was different. the second solution lock time should be faster than the first solution.

        I guess as the fPDX decrease, the PLLx_WND_SIZE should increase. the information can be found at LMX2581 datasheet. It was dependent on the implementation. if the LMK04816 follow the same architecture, the similar function should be followed.

      Could you clarify the relationship between the PLLx_WND_SIZE and fPDX? in alternative, could you please explain more about the DLD circut more.

    Regards

    Ed