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CDCE913/925 bahaviour on input clock switchover

Janusz Uzycki
Prodigy 20 points
Other Parts Discussed in Thread: CDCE913, CDCM6208

Hello,

I'm interested in CDCE913 chip series stability on input clock (LVCMOS) switching between asynchronous 10MHz frequency references:

- What will happen with output phase? Will it be continued smoothly or jump in an extreme case?

- What the PLL's filter time constant value and maximum VCO's drift are?

- Does the PLL require glitch-free mux or simple mux is enough?

I need to estimate MTIE (and max.jitter) of the PLL output in the worst case.

Can you advice me preffered chip for such low cost application?

best regards

Janusz

  • 0
    TI__Mastermind 24205 points

    Hi Janusz,

    There is no mechanism in CDCE913 device to control the phase hit during input switchover. The phase/frequency slew will depend on the PLL loop bandwidth and more than likely the VCO will drift significantly if a phase hit occurs on the input during a reference switchover.

    On the CDCM6208 which has input switchover built in, there is some room to reduce the loop bandwidth to ~100Hz and limit the frequency drift. The VCO gain is ~200 MHz/V and the GUI can be used to figure out the loop filter parameters that are required to set the low loop bandwidth

    Beyond that, you are better off looking for a Digital PLL with Hitless switching feature (unfortunately at this point of time, TI does not have discrete digital PLLs in their portfolio)

    Regards

    Arvind Sridhar

  • 0 in reply to Arvind Sridhar
    Prodigy 20 points

    Thanks Arvind for the hint.

    I've considered the CDCM6208 and other phase-hitless DPLL chips but they are rather targeted to telecom market (stratum 2-3).

    The solution must be lower cost. CDCM6208 cost is near to limit.

    I consider an additional simple PLL before CDCE913 in order to limit the slew rate on switchover.

    Could you tell me what CDCE913's bandwidth or other PLL's key-parameters are?

    I can't see them in its datasheet and they are useful to calculate the primary PLL parameters.

    kind regards

    Janusz