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LMK04906 - PLL2 settings

Bud Patterson

Prodigy 20 points

Other Parts Discussed in Thread: LMK04906

Hello,

We are having trouble translating settings for PLL2 from the LMK04906 evaluation board to our circuit. We are using the part in dual loop mode with a 40 MHz VCTCXO as the VCXO for PLL1.

We have populated the 40 MHz VCTCXO on the LMK04906 evaluation board and the performance is satisfactory with PLL2_C4_LF set to 146 pF. However, when we try to use these settings on our board, which is electrically identical, PLL2 is unstable and does not lock. Adjusting the charge pump current has no effect.

Your assistance is appreciated!

Best Regards,

-Bud

over 11 years ago

0 Arvind Sridhar over 11 years ago

TI__Mastermind 24205 points

Hi Bud,

Please share the clock portion of your schematic and the datasheet for the VC-TCXO?

Regards

Arvind Sridhar

0 Bud Patterson over 11 years ago in reply to Arvind Sridhar

Prodigy 20 points

Hi Arvind,

Thanks for the quick response.

Please find the attached data package, which includes our own phase noise plot for the VCTCXO.

One thing to note is that we depopulated the external loop filter on CPOUT2 of the EVM to match our design.

Best Regards,

-Bud

LMK_Investigation.zip

0 Arvind Sridhar over 11 years ago in reply to Bud Patterson

TI__Mastermind 24205 points

Hi Bud,

Sorry for the late reply. I need some more information from you.

1) Input frequency and Type on CLKin - Sig Gen on CLKin1 and LVDS signal on CLKin0?

2) VC-TCXO Output type (Looks differential -LVDS)?

3) Output Clock Frequency (ies)?

4) PLL2 loop filter components?

The VCTCXO phase noise looked sub-optimal. What is the VCTCXO part number and what equipment are you using to measure phase noise?

Regards

Arvind Sridhar