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LMK03806 SYNC signal

Markus Mettenleiter
Prodigy 30 points
Other Parts Discussed in Thread: LMK03806

Hi,

I'm using the LMK03806 as multiple clock source. For this application it's important to make use of the "SYNC" input in order to start multiple clocks with defined phase relation. According to the data sheet this is very simple: when SYNC is asserted, all sync-selected output clocks go low, after de-assertion they start with defined phase relation.

In fact this doesn't seem to work at all: whatever clock is selected to be SYNC'd (by setting the appropriate NO_SYNC_CLKout bit to zero) is just "dead" all the time - no matter which level or edge is applied to the SYNC input. The only way to get my clocks working is to disable the SYNC  (by setting the appropriate NO_SYNC_CLKout bit to one) - the I get the clock signals, but they are not in defined phase-relation.

Why doesn't the SYNC seem to work - what I'm doing wrong here ????

Thank's a lot,

Markus

  • 0
    TI__Mastermind 32575 points

    Are you meeting the VIH/VIL levels defined for the SYNC input?

    Have you tried changing the SYNC_POL_INV bit?  When SYNC_POL_INV = 1, SYNC pin is active low.  Otherwise, it is active high.

    Is the PLL indicating lock on the Status pin, and verified by measuring the expected frequency on the outputs?

    Is SYNC_POL_DLD = 0 to prevent forcing SYNC until the PLL is locked?

    Regards,
    Alan

  • 0 in reply to Alan O
    Prodigy 30 points

    Alan, thank you for your quick reply!

    The SYNC level and polarity are ok, actually setting the SYNC_PLL_DLD=1 is the problem. As soon as I set it =0, the SYNC and clocks are working properly!

    The question is why SYNC_PLL_DLD=1 is inhibiting the clocks despite the PLL being properly locked ?!
    I'm very sure about the PLL being locked because the Ftest/LD output is active (set to PLL DLD) and steady (checked with scope).The output frequencies are as expected and the TIE (jitter) is around 0.8ps rms - rather stable.

    Just can't imagine how the PLL could not be locked. But if the PLL is locked how can setting the SYNC_PLL_DLD=1 disable all my clock outputs ?

    Best regards,
    Markus

  • 0 in reply to Markus Mettenleiter
    Prodigy 30 points
    Alan,
    I was noticed that this case is still pending.
    However, I've found the answer by myself:

    The solution is to set the SyncModeForced ( R12[23] ) bit = 0, then everything works fine.
    According to the datasheet setting this bit =1 means that SYNC will be engaged until PLL locks. To me this means that the SYNC automatically will be asserted as long as the PLL is not locked. But obviously this also PREVENTS engaging the SYNC signal in case the PLL is already locked!

    This is a rather odd feature: keeping SYNC asserted as long as the PLL is not stable makes sense, but what's the point of preventing any later assertion of SYNC after the PLL has been locked ? Probably this is just a logic bug, however it would be very helpful to clarify the description of this particular bit in the spec sheet ...

    Regards,
    Markus