LMK04828 questions

Hello Iouri,

1. In case you want to use the LMK04828 in dual loop mode as a jitter cleaner, you need to connect a reference to CLKinX in order to close the loop of PLL1 and to jitter clean the reference. Otherwise you just have a free running single loop device.

2. With Webench Clock Architect http://webench.ti.com/webench5/power/webench5.cgi?app=clockarchitect&input1=25&output1=24&output2=27&output3=25 you can see whether your frequency plan can be achieved with LMK04828. Click on "Advanced" and enter "LMK04828" without " in the Part filter. Webench can also simulate the Phase noise performance of the device and provide you with the correct loop filter components.

Another option is to directly using codeloader, which is the EVM programming software. This tool does not have a "frequency planner" but it helps to generate the register settings. 

Please let me know if you have further questions.

Best regards,

Julian

Hi Julian,

Thank you for your replay.

I have few more questions:

1. What is best way to select charge pump1 external components schematic, and what is best way to calculate them?

2. How to select optimal charge pump current?

3. I am not able to get PLL 1 locked, I am using 10MHZ external reference with 100MHZ VCXO, R register set 10 and N register set 100. I am able to PLL1_N and PLL1_R outputs and they seems to be correct? Can you please advise what else I should check

4. Divider (1-32) at every DCLK output doesnt seems to work, no matter what value I placing I am always getting 100MHZ output DCLKoutX_MUX register set 0, can you please advise where else I should look?

Thank you,

Iouri

Hello Iouri,

1. you can use CDT http://www.ti.com/tool/clockdesigntool.

It helps with loop filter design. In the Loop filter Design window, you can specify the requested Bandwidth and phase margin -> which will provide a good loop filter component selection.

2. optimal CP current depends on the PFD update frequency and the loop filter components. I would recommend a CP of ~ 0.85mA and and PFD update frequency = 1MHz.

3. Are you using the Codeloader GUI to program the device? If yes, please make sure in the "Bits/Pins" tab that CLKinX is enabled and also check that the CLKinX_R divider is set correctly. The PLL1 tab only updates CLKin1_R divider.

4. if you are using Codeloader for the programming, you need to press Enter, if you change a value in the output divider field.

best regards,

Julian

Hi Julian,

Thank you for your replay. I am using custom hardware to program LMK, if there are other options for question 3 and 4?

Thank you,

Iouri

Hello Iouri,

if there is always 100MHz at the outputs no matter what you program, it appears that there is some false register writes.
Could you please share a register write and read for one of those registers 0x100, 0x108, 0x110, 0x118, 0x120, 0x128, or 0x130?

For PLL1 lock, try to disable HOLDOVER_EN, HOLDOVER_FORCE. Set PLL1_WND_SIZE to maximum.

best regards,
Julian

Hi Julian,

Thank you for your replay.

here the register 0x120 write 0x11 read 0x11.

Also what exactly Input/output drive level mean (bit5,6) in register 0x120?

Still no luck I am getting 100MHZ signal

PLL1 I tried to disable bits what you said and no luck again:(

Also I try to disable: pretty match everything on Holdover and LOS areas still no luck:(

Any other idea 

Thank you for your support.

Regards,

Iouri