Hello,
We have a recently developed a system with Master/Slave CPRI devices running on Xilinx FPGAs. The slave board is using the LMK04806 clock chip. Do you have any recommendations regarding the usage/configuration of this chip?
I ask because in the testing of the system, I’ve found that the Holdover mode is causing problems in the power-up, link initialization of the slave device. After power-up, and the FPGAs are configured, they program the clock chips on their own boards. The master boards uses a CDCE62005 chip. The slave board uses the LMK04806. Then, the CPRI cores attempt to establish the link (9.8 Gbps over fiber). The master device shows that it has reached the Operational State, but the slave device is stuck in the Protocol Version Setup State. I noticed that the LMK04806 was in the Holdover mode. I don’t believe that should be correct. The link has not ever been established, so there is no accurate clock to holdover and maintain. So, when it goes into holdover after power-up, it’s forcing an output clock that is off-frequency. Right?
I disabled the holdover mode, and now things work correctly after power-up. I’d like to know if there are any suggested programming sequences or design tips for this kind of application. I’d like to use the holdover, but I don’t think it should be enabled until after the CPRI link has been established.
Thanks!
Luis Cordova
