LMK04828B PLL operation without External VCXO

Hi Soumya,

The LMK04828 can be used in single PLL mode in which PLL1 is bypassed - the reference would be supplied to the OSCin pins to drive PLL2. Am I understanding your query correctly?

Gabe

Hi Gabe Ayala,


Thank you for your response.

You got my query correctly.

I am using a input reference clock of 25MHz. As per your suggestion PLL1 shall be bypassed. That means I need to provide the reference clock of 25MHz at the OSCin pins instead of CLKin pins. shall I able to achieve 2400MHz VCO frequency by using 25MHz reference clock with one stage PLL.

And one more constraint is the three clock input options i.e. CLKin0, CLKin1 & CLKin2 won't be available for me.

Regards

Soumya S

Hi Gabe Ayala,

I want to know what will be the jitter performance of the LMK04828 PLL without VCXO.

Regards
Soumya S
Hardware Design Engineer

Hi,

Is it possible to generate 2400MHz clock, by providing 25MHz TCXO clock at the OSCin pin of the LMK04828 PLL ?

Regards,
Soumya S

Hi Gabe Ayala,

I have used the clock design tool.

By setting the loop filter1 to 0 Hz LBW I got a phase noise of -995.23 dBc/Hz. Is that acceptable ? I need to use this PLL for the SYSCLK of ADC12J400 ADC which compliant with JESD204B standard.


I Planned to use 25MHz clock at OSCin pin of the PLL & the CLKin shall be floating.
But when I removed CLKin frequency value in the clock design tool, I was unable to enter the VCXO frequency.

Is it mandatory to provide CLkin ?

Regards
Soumya S

Dear Gabe Ayala,

Thank you for the reply.

As per your suggestion I need to adjust the loop filter 2 i.e. the loop filter at CP2 output to achieve  less phase noise in the CLKOUT pin.

Correct me if I am wrong.

Is it mandatory to provide reference clock at the  CLKin pin for this configuration ?

Regards

Soumya