CDCE906 - PLL Lock - Time

Hirotaka Matsumoto

Other Parts Discussed in Thread: CDCE906

Hi all

Would you mind if we ask CDCE906?

The datasheet on figure34 shows PLL Lock - Time from 81MHz to 297MHz.
So, does it mean that PLL Lock - Time has proportionality?

We need your help.

Kind regards,

Hirotaka Matsumoto

over 11 years ago

0 Hirotaka Matsumoto over 11 years ago

Guru 27595 points

Hi all,

We guess that your team is so busy, but if you have some advice could you let us know it?

Kind regards,

Hirotaka Matsumoto

0 Arvind Sridhar over 11 years ago in reply to Hirotaka Matsumoto

TI__Mastermind 24205 points

Hi Hirotaka San,

Sorry for the delay in response. The short answer to your question is that the PLL Lock time will be proportional to the delta between the initial and target frequencies. The settling time will also depend on the loop bandwidth and damping factor/phase margin.

Regards

Arvind Sridhar

0 Hirotaka Matsumoto over 11 years ago in reply to Arvind Sridhar

Guru 27595 points

Arvind san,Ok, thanks.Hirotaka Matsumoto

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CDCE906 - PLL Lock - Time