I am looking for a solution to the following:
An LVDS pulse is provided by an FPGA that is 200MHz (5 ns). A DAC is providing two inputs that are a DC bias 0-5V and an amplitude adjustment also 0-5 V. The circuit would allow amplitude adjustment of the FPGA clock and a DC bias adjustment of the FPGA clock without changing the pulse width (5 ns). The output of this circuit would be 0-1V. As the DAC is changed the output pulse would reflect the adjustment.
Thanks,
Earl
