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lmx2581 optimization

David Schriebman63
Prodigy 40 points
Other Parts Discussed in Thread: LMX2581, LMX2571

Hello,
We are looking to minimize the spurs and phase jitter on the lmx2581 we are designing into a product. We are using a 50MHz reference TCXO and are trying to synthesize several frequencies, the first of which is 49.9768MHz, the second is 99.9536MHz.

When synthesizing a frequency of 99.9536MHz, we are seeing two sideband spurs 46.3KHz from center frequency, and down 79.6dBc. Any assistance you can give for settings which may reduce these spurs further would be most appreciated. Thank you.

We are using 50 ohm resistive pullups on the outputs, and the current register settings are as follows (decimal value is listed before register bit description):

Register 15:
0: VCO_CAP_MAN
128: VCO_CAPCODE

Register 13:
4: DLD_ERR_CNT
32: DLD_PASS_CNT
5: DLD_TOL

Register 7:
0: FL_SELECT
2: FL_PINMODE
0: FL_INV
1: MUXOUT_SELECT
0: MUX_INV
1: MUXOUT_PINMODE
2: LD_SELECT
0: LD_INV
3: LD_PINMODE

Register 5:
0: OUT_LDEN
0: OSC_FREQ
0: BUFEN_DIS
1: VCO_SEL_MODE
mux_vco_div: OUTB_MUX //this is 0 or 1 determined dynamically
mux_vco_div: OUTA_MUX
0: 0_DLY
0: MODE
0: PWDN_MODE
0: RESET

Register 4:
4: PFD_DLY
0: FL_FRCE
64: FL_TOC
31: FL_CPG
0: CPG_BLEED

Register 3:
VCO_DIV< 15: OUTB_PWR
15: OUTA_PWR
1: OUTB_PD
0: OUTA_PD

Register 2:
0: OSC_2X
1: CPP
4000000: PLL_DEN

Register 1:
18: CPG
VCO_CORE_SELECT: VCO_SEL //this is 0-3 determined dynamically
PLL_NUM1: PLL_NUM_MSB //this is determined dynamically
3: FRAC_ORDER
1: PLL_R

Register 0:
0: ID
3: FRAC_DITHER
0: NO_FCAL
PLL_N: PLL_N //this is determined dynamically
PLL_NUM2: PLL_NUM_LSB //this is determined dynamically

  • 0
    TI__Mastermind 27691 points

    David,

    A few things:

    1.    Use VCO_SEL = VCO3 and use frequencies with VCO3 whenever possible as this has the lowest spurs, Except if you can avoid an integer boundary by using a differnt core.

    If you are synthesizing freqeuncies in the 100 MHz range, there should be many options, so choose one that puts the VCO frequency far from an integer boundary.

    2.    Try to keep VCO away from integer multiples of the phase detector frequency, unless you can make it an integer multiple exactly.

    3.     For your frequency of 99.9536MHz, you see a spur at 46.3 kHz.  This looks like:

    Fout % Fosc = 99.9536  % 50= 46.3 MHz

    4.  Also be aware that we newly released the LMX2571.   The disadvantages of this part vs. the lMX2581 are that it can only synthesize frequencies up to  1350 MHz and the VCO noise is about 4 dB worse.  However, it has lower spurs, better PLL phase noise (by about 3 dB), and lower current (about 39 mA).  I'm thinking that if you are focused on jitter, then maybe the better PLL noise might be a better benefit than the better VCO phase noise.   You can simulate and compare with our WebBench Clock Architect or Clock Design Tool.

     

    Regards,

    Dean

    Now this looks like interaction between the input and output signal.  Consider the following of:    increase slew rate of Fosc Signal, decrease amplitude of Fosc signal, use better isolation between supplies for Fosc and Fout (especially pull-up resistor).