LMX2492

David,

The lock time is almost completely governed by the loop bandwidth of the loop filter, which is set by external components.   Making a wider loop bandwidth speeds lock time, but degrades phase and spurs.

If one was to disregard phase noise and spurs, you can design a very widebandwidth filter to lock in a few us, but you probably would decide that you do care somewhat about phase noise and spurs and then this becomes a few 100 uS.

For the ramping features, we have done a 10 us ramp with a 500 kHz loop bandwidth and the spurs/phase noise were not too bad.  But in the case of ramping, the PLL doesn't have to fully lock, so this is why these times are pretty fast.

Regards,

Dean