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LMK04803 locking problem

Gergely Nemeth
Prodigy 50 points
Other Parts Discussed in Thread: LMK04803, CODELOADER

Hi,

We have the following issue with the LMK04803 clock-jitter-cleaner.
We use the chip according to the attached schematic (pdf).
Our problem is, the the PLL does not lock in 0-delay mode - we did not try non-0-delay.
First we experienced the issue with the "2nd stage" (U101), the first IC (U100) was in clock-distribution mode.
In this case there was rarely lock - for U101 -, but only after power-reset, never after soft-reset.
Then programming the first (U100) IC to "dual PLL w 0-delay" mode there was no lock at all.
U101 programming would start after U100 lock, but never happened.
I also attached the configuration files.

What could be the problem?

Another remark:
I used Codeloader for register value checking.
The program does not take in account 0-delay mode for feedback path divider calculation.


Thanks,

Greg

EL-24-80-00_DCS7.pdf

Fullscreen CJC_STG1_0-delay_U100.txt Download 
R0 (INIT)	0x80160100
R0	0x00140100
R1	0x00140101
R2	0x00140102
R3	0x80140103
R4	0x00140104
R5	0x80140105
R6	0x11110006
R7	0x00110007
R8	0x00110008
R9	0x55555549
R10	0x10005D0A
R11	0x1400200B
R12	0x1B0C006C
R13	0x0303824D
R14	0x0300000E
R15	0x0000800F
R16	0x41550410
R24	0x00000058
R25	0x01010019
R26	0xAFA8001A
R27	0x1C00009B
R28	0x0020009C
R29	0x0100005D
R30	0x0100005E
Fullscreen CJC_STG2_0-delay_U101.txt Download 
R0 (INIT)	0x80160100
R0	0x00140140
R1	0x00140141
R2	0x00140142
R3	0x80140143
R4	0x00140144
R5	0x00140145
R6	0x11110006
R7	0x00110007
R8	0x11110008
R9	0x55555549
R10	0x10005C0A
R11	0x4400200B
R12	0x130C006C
R13	0x0303800D
R14	0x0300000E
R15	0x0000800F
R16	0x01550410
R24	0x00000058
R25	0x01010019
R26	0xAFA8001A
R27	0x100000BB
R28	0x0020011C
R29	0x000000BD
R30	0x0100003E

  • 0
    TI__Mastermind 20900 points
    Hello Greg,

    it seems to me that the PLL2_N_CAL register setting needs to be changed from 10 to 2 at U100.

    best regards,
    Julian
  • 0 in reply to Julian Hagedorn
    Prodigy 50 points

    Hello Julian,

    thanks for your reply.
    R29 is set to 0x0x0100005D, that means:
    - OSCin frquency 63-127 MHz
    - PLL2_N_CAL divider 2
    according to datasheet.

    Or am I missing something?

    Best regards,
    Greg

  • 0 in reply to Gergely Nemeth
    TI__Mastermind 20900 points
    That is correct. Did the change help?
  • 0 in reply to Julian Hagedorn
    Prodigy 50 points

    Hi Julian,

    your suggestion did not help, because PLL2_N_CAL was already 2.

    We found a solution last friday. We had to lower VCO frequency from 2 to 1.9 GHz.

    What do you think why does not it work at 2 GHz?

    Best regards,
    Greg

  • 0 in reply to Gergely Nemeth
    TI__Mastermind 20900 points
    Hi Greg,

    can you send me the new register settings, then i can have a look.

    Julian
  • 0 in reply to Julian Hagedorn
    Prodigy 50 points

    Hi Julian,

    here is the new configuration file for U100.

    Greg

    Fullscreen U100_1900MHz.txt Download 
    R0 (INIT)	0x80160100
R0	0x001404C0
R1	0x001404C1
R2	0x001404C2
R3	0x80140103
R4	0x001404C4
R5	0x80140105
R6	0x11110006
R7	0x00110007
R8	0x00110008
R9	0x55555549
R10	0x1000490A
R11	0x1400200B
R12	0x1B0C006C
R13	0x0303824D
R14	0x0300000E
R15	0x0000800F
R16	0x41550410
R24	0x00000058
R25	0x01010019
R26	0x8FA8001A
R27	0x1C00009B
R28	0x0020009C
R29	0x0100027D
R30	0x0100027E

  • 0 in reply to Gergely Nemeth
    TI__Mastermind 20900 points
    in this new configuration the VCO_DIV is disabled. Also the PLL2 PFD frequency is equal to the reference frequency. Therefore, PLL2_N and PLL2_N_CAL should be the same and PLL1_N=1.
    The first config you send should lock if you change PLL1_N=2.
  • 0 in reply to Julian Hagedorn
    Prodigy 50 points
    Hi Julian,

    in the original configuration PLL1_N is 2.

    We checked the PLL divider values several times.
    As I wrote in my first post, we had lock sometimes, but only after powerup.
    We measured PLL frequencies via status_LD, and it seemed that VCO frequency is stuck at about 1940 MHz, and cannot reach 2000.

    The new configuration works.
    PLL2_N and PLL2_N_CAL is the same: 19.
    PLL1_N is 2 because PLL1_R is also 2 .
    VCO Frequency / CLKoutX_Y_DIV / PLL1_N = CLKinX Frequency / CLKinX_PreR_DIV / PLL1_R
    1900 / 38 / 2 = 50 / 1 / 2