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Building Ultra-Low Jitter clock tree

Thom Lauret
Prodigy 60 points
Other Parts Discussed in Thread: LMK04828, LMK03806, LMK03328

Hello,

Please evaluate this clock tree design and help me optimize, minimize jitter and use complimentary components.

*I would like to know a TI alternative to HMC1031MS8E

Either the AOCJY4A-10.000MHz-SW or an external 10MHz frequency reference locks long term stability to the VX-805 VCXO through HMC1031MS8E. The 100MHz output of the VCXO then supplies a LMK04828. That then supplies 100MHz to daughterboards with LMK04828 and LMK03806. Is it ideal to cascade the LMK04828 part or should we have used a clock buffer ?

Please advise

Thanks !

  • 0
    TI__Mastermind 24205 points

    Hi,

    What are the desired output frequencies in your system? Please specify the integrated RMS jitter requirements for the output clocks.

    Also, how are you planning to feed two inputs to the HMC PLL that supports only a single input reference? Is there a MUX prior to the HMC device that is doing the reference clock selection/switching?

    Regards

    Arvind Sridhar

  • 0 in reply to Arvind Sridhar
    Prodigy 60 points
    Hi Arvind,

    The VCXO output and all the outputs on the first LMK04828 are 100MHz. The outputs from the second LMK04828 and LMK03806 are variable for this SDR application.

    RMS jitter requirement for devices supplied through the second LMK04828 and LMK03806 is 100fs however 25fs is highly desirable.

    The MUX we plan on using is IDT 831721I

    Thanks
  • 0 in reply to Thom Lauret
    TI__Mastermind 24205 points

    Hi Thom,

    Sorry for the late reply on this one. Are you using the LMK04828 (first and second) in single-loop (PLL2 only) mode?

    Looking at your clock tree, I would recommend considering operating the first LMK04828 in dual-loop mode (if not already) and eliminate the need for the HMC1031 device). PLL1 on LMK04828 supports multiple inputs and can handle the switching between them (eliminating the need for the IDT Mux). The VCXO can be made as input to the second PLL (PLL2) on LMK04828

    The outputs from the first LMK04828 can be input to a device like LMK03328 (http://www.ti.com/lit/ds/symlink/lmk03328.pdf) to potentially replace the functionality of the LMK03806 and the second LMK04828. Buffers (lower cost) can then be added to fanout the required number of outputs.

    Regards

    Arvind Sridhar

  • 0 in reply to Arvind Sridhar
    Prodigy 60 points
    Hi Arvind,

    What is the difference between the CLKin0 and CLKin1 ? The datasheet lists CLKin1 as a backup oscillator but is there a difference between the routing of the clock domains (is there a clear preference for use of CLKin0)?

    Is there any configuration required with CPout1 and is this suitable for a high-precision OCXO?

    Thanks
  • 0 in reply to Thom Lauret
    TI__Mastermind 24205 points

    Hi Thom,

    Sorry for the late reply yet again! 

    CLKin1 is shared for use as an external 0-delay feedback (FBCLKin), or for use with an external VCO (Fin). The structure of the reference path and input mux is similar between CLKin1 and CLKin0. There is no preference one way or the other

    You would need to install external loop filter components on your board connected to CPout1. The loop filter component values can be computed using the National Clock Design tool (link below). Just enter your desired input and output frequencies and the tool can aid you with the part selection, phase noise simulation and loop filter configuration for achieving the desired bandwidth and phase margin. If you can provide me the Input and Output frequencies, I would be happy to recommend a loop filter configuration for you using LMK04828.

    www.ti.com/.../clockdesigntool

    Regards

    Arvind Sridhar