PLL Advice

Anthony Rowe

Other Parts Discussed in Thread: LMX2541, LMX2571

I am interested in generating a 38.4MHz clock source from a rubidium oscillator that will output either 10MHz or 16.384MHz. I was thinking about using something like an lmx2541 or lmx2571 to do this synthesis. I'm most concerned about minimizing jitter and making sure the 38.4MHz output is as stable as possible (maintaining much of the atomic stability). I'm not an analog expert by any metric, so any advice would be greatly welcomed.

Thanks,

Anthony

over 10 years ago

0 Anthony Rowe over 10 years ago

Prodigy 125 points

Also, is there any advantage in terms of multipliers etc of designing around one frequency or another given the two options...

0 Dean Banerjee over 10 years ago in reply to Anthony Rowe

TI__Mastermind 28031 points

Anthony,

If I get the question, you are wondering if there is an advantage of using a PLL for this frequency. I assume that your input frequency is very clean and the advantage of using a PLL is that you could producemany different frequencies with good phase noise, although it is probably not going to be quite as good as your rubidium standard.

At closer offsets inside the loop bandwidth, it should be only slightly worse on the order of a dB or so. For farther offsets, teh VCO will probably not be as good as your rubidium standard and the phase noise will be worse.

Regards,
Dean

0 Anthony Rowe over 10 years ago in reply to Dean Banerjee

Prodigy 125 points

Thanks for the info. In our case, we need a PLL to transform the rubidium source from 10 or 16.384MHz to 38.4MHz. I'm looking for advice on the best way to do that conversion without degrading the quality of the clock input. Does that make sense? I can also choose 10MHz or 16.384MHz if that matters.

-Anthony

0 Dean Banerjee over 10 years ago in reply to Anthony Rowe

TI__Mastermind 28031 points

Consider using the LMX2571 with 10 MHz. Make the phase detector frequency 10 MHz and make the VCO frequency 4300.8 MHz. Then use the output divider to divide this by 7*16 = 112 to get 38.4 MHz.
You do need a fractional mode, but the fraction is 1/25 and there will be a spur at 400 kHz away, although it should be pretty far down.
REgards,dean

0 Anthony Rowe over 10 years ago in reply to Dean Banerjee

Prodigy 125 points

Awesome, thanks for the input.

0 Anthony Rowe over 10 years ago in reply to Anthony Rowe

Prodigy 125 points

Got the LMX setup working well being feed from our external clock. I assume you can't use both PLL outputs at the same time? Are there any tricks for reducing jitter on the outputs?

Thanks,

-Anthony

0 Noel Fung over 10 years ago in reply to Anthony Rowe

TI__Guru** 119610 points

Hi Anthony,

what is the integration bandwidth you concern most for the jitter? if it is below 100kHz offset, you can make the loop bandwidth > 200kHz and phase margin between 30deg and 40deg.

Clock & timing

Clock & timing forum

PLL Advice