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LMK04828: PLL1_LD_MUX settings and PLL2 Lock Detect

Atmeg
Intellectual 870 points

I'm using Status_LD2 pin for SPI MISO and Status_LD1 pin for led indication. I'm reading PLLs lock status from 0x182 and 0x183 regs.

When PLL1_LD_MUX is configured to 0x2 or 0x3 (PLL2 DLD or PLL1 & PLL2 DLD) 0x182/0x183 showing both PLLs are locked. When PLL1_LD_MUX is configured to any other value 0x182/0x183 showing PLL1 is locked but PLL2 is not. It seems that PLL2 lock detector disabled if it is not used for output to Status pin.

  • 0
    TI__Mastermind 28560 points

    This is correct.  We will be updating the datasheet to reflect this.  PLL2 DLD circuitry is only powered up when the PLL2 DLD is selected by one of the output pins.  You'll notice an ~2 mA savings when PLL2 DLD is not active.

    Unfortunately the only way to power up the PLL2 DLD is to set the output MUX vs. only reading its status through the read back register.

    Also note that RB_PLL#_LD is 1 for PLL# DLD high.  Not 0.


    73,

    Timothy