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LMX2571 register write delay

Other Parts Discussed in Thread: LMX2571

Hello,

I am looking for specifications regarding register write delays in the LMX2571. From datasheet page 7 I read: "On the rising edge of the LE signal, the data is sent from the shift register to an active register."

To measure the additional register write delay there might be, I repeatedly wrote to register R39, toggling SDO_LD_SEL (to toggle the Lock Detect LED), while monitoring the LE, CLK and LD-Output on a scope. What I noticed: Contrary to the datasheet, LD toggles on the last rising edge of CLK instead of the rising edge of LE. After the last rising clock edge I see a delay of about 4.5ns.

Can you confirm this is actually a datasheet eror and possibly give specifications for additional expected delays from 'register write' (last rising edge of CLK) to 'register update'? I'm especially interested in extra delays when writing R33 and/or R2+R1.

Thank you,

Stefan

  • Hi Stefan,
    Although it appears that the register is updated by the rising edge of CLK, a valid register write requires a rising edge of LE to complete. If you want to make multiple register write faster, make tCES, tES and tEWH close to the min. requirement.
    We did not characterize the response time between register write and update. According to the designer, it should be in a few nanosecond.
  • Hello!

    For our application, not only speed is necessary, but precise timing. I understand that for a complete read, LE is needed and can conform to that specification. Can you confirm that the actual shift register -> register latching is happening on the last CLK rising edge for every register, just as I observed with R39?


    Regards,

    Stefan

  • Stefan,
    I confirmed with the designer and indeed you are correct. The latching actually happens on the last CLK rising edge of every register. The LE pulse serves as a reset to signify the start of the next register. In fact, the LMX2571 has an "autoincrement" feature, that means that you can concantenate multiple adjacent registers by excluding the LE pulse.
    Regards,Dean
  • Hello Dean,

    thank you very much, this information was very helpful to me!


    Regards,

    Stefan