Other Parts Discussed in Thread: LMX2571
Hello,
I am looking for specifications regarding register write delays in the LMX2571. From datasheet page 7 I read: "On the rising edge of the LE signal, the data is sent from the shift register to an active register."
To measure the additional register write delay there might be, I repeatedly wrote to register R39, toggling SDO_LD_SEL (to toggle the Lock Detect LED), while monitoring the LE, CLK and LD-Output on a scope. What I noticed: Contrary to the datasheet, LD toggles on the last rising edge of CLK instead of the rising edge of LE. After the last rising clock edge I see a delay of about 4.5ns.
Can you confirm this is actually a datasheet eror and possibly give specifications for additional expected delays from 'register write' (last rising edge of CLK) to 'register update'? I'm especially interested in extra delays when writing R33 and/or R2+R1.
Thank you,
Stefan