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1 pps CDCLVP1204 application

jaime martin
Intellectual 515 points

Other Parts Discussed in Thread: CDCLVP1204

Arvind, being solved the previous issue about a CDC1204 application i would like to ask you about another one.

We are involved in a new design of an auxiliary module managing sinc signals of 1Hz (1pps) and 10 MHz), that will be auxiliar via DPLL to the main system clock.

Both signals are in digital format LV3.3V originally single ended.

We need some functions as demultiplexer/switch (dual input/one output), mux (one input/2 or 3 outputs) and so on.

I am considering the use of the CDC1204 for the use as demux, being able to select one of two inputs.

My doubt is about the use of the chip, and in general of the LVPECL, for frequencies as low as 1Hz. The reason is that this is the frequency of the pulse but we need to have the fastest rise time as possible. the output of this system is directed to a DPLL that will geerate the system clock and so it is very important for jitter concerns not to add jitter either to the 10 Mhz and to the 1pps signals. Being the 1pps signal positive pulses once every second, but with very fast rise time, i guess that I can use these technology at leats working with signals DC coupled and limitig their swing to 3.3V, is it correct? As the duty cycle uses to be small, the only "special" thing of the signal is that it stays near one second each period at 0V.

Thanks in advance

  • 0
    TI__Mastermind 24205 points

    Hi Jaime,

    CDCLVP1204 should be able to handle a 1pps signal on its input as long as the edge rate (20%-80%) is > 1.5V/ns. The recommended LVCMOS input termination is shown in Figure 14 in the datasheet. The LVPECL outputs on the device should be able to work down to 1pps as well.

    Regards

    Arvind Sridhar

  • 0 in reply to Arvind Sridhar
    Intellectual 515 points

    For the typical 1pps input the 1.5v/ns figure is very much in the range of the real signal, it will be roughly that. I measured about 3ns 1 to 3v. What will happen in tbis boundary?

  • 0 in reply to Arvind Sridhar
    Intellectual 515 points
    Hi again Arvind. I tested the solution with an evboard and it works, but there is a crazy overshoot at the output. I checked that, when driving the LVP1204 with 50 ohm termination resistors, our PPS signal is very pure, no overshoot at the very 1204 input, It seems that the gain is so high. The input rise time is only about 1ns, no overshoot; the output is even faster but it presents dumped rebounds that start at +/-0.5V both in the rise and the fall, then go diminishing. Even being differential I wonder that the next stages will occur in false transitions. There is no transient supressing that you can do at the input as the input is clean of vershoots, they appear only in the 1204 outputs. Any suggestion?
  • 0 in reply to jaime martin
    TI__Mastermind 24205 points

    Can you email me your clocking schematic for review: arvind.sridhar@ti.com?

    Regards
    Arvind Sridhar

  • 0 in reply to jaime martin
    Intellectual 515 points
    Thank you very much. It will not be necessary as there was a mistake in the test, the output block capacitors had not been bridged and that together with the high impedance probe caused the ringing and a DC change of course. I realized that the previous measurement were done with the ev board output caps (they are not problem in the previous applications, but with this signal one is forced to do every coupling in DC, as it is foreseen in the design. That was the reason that the scope had to be used in hign impedance and this caused the ringing. It is curious to note that when we used the part with 10 MHz and 70 Mhz signals, even if we use output DC coupling in the real design, the tests with the evboard were OK with the AC coupling that the ev board is prepared for.

    Now the output signal measured with each line 50 ohm DC termination at the scope has not ringing at all, the output levels are the real LVPECL and the rise time that we can measure is identical to the input one (1ns). It is surely faster as the spec is 200ps 20% to 80% and we are not able to measure it with our scope... it gives the same result with the CMOS input and the LVPECL output to reduce the rise time is the main purpose of the use of the stage. It is a 600MHz scope so we maybe need a larger BW one.

    Best,
    JM
  • 0 in reply to Arvind Sridhar
    Intellectual 515 points

    The signal is fair good and with a faster scope I was able to measure a 350ps ps rise time, which is much closer to the spec, while the input signal slews up in no less that 1.5ns. There is no output overshoot at all when the output is DC coupled and properly terminated.

    By the way just a detail on the schematics. I drive the pps input to a 50 ohm to ground (not to VacREF) resistor at the INP input, while for comfort I keep the INN tied via 50ohm, to VacREF that is AC decoupled to ground, as this is a convenient midpoint bias for the unused input. But in the final application schematic, as the LVCMOS input will not be 50 capable, the plan was: the input 50 ohm load will be removed or replaced by a larger resistance load (maybe 1K, or an open); while the unused input was to be biased with resistors from Vcc, equaling the overall Zg of each input.

    My question is about the chance to save the unused input's bias resistors, using the VacREF pin also in the final application, only for that input, and replacing its 50 ohm load (as per the ev. board) with a resistor in the hundreds to K ohms range like the one the driver can afford in the used input.