Other Parts Discussed in Thread: LMK04828, ADS54J54
Hi
This question is regarding to LMK04828 setting (especially SYSREF)
I have ADS54J54 & LMK04828 on the board which is customized with Xilinx Virtex 7 2000T (JESD204B)
The design is based on following setting
Sampling rate 368.64M
184.32MHz x 20bits (8b/10b encoding)
Decimation
Using 1 lane
If there is some delay on AD data channel, (between 'ab' & 'cd' , or sometimes all channel 'a','b','c','d' have different delay)
I think that ADC hasn’t been synchronized with JESD204B (subclass1)
I am assuming that the reason for “not synchronized” is due to sysref.
How big should be fine for LMK sysref? In order words, how big should I set up SYSREF Divider?
Thank you
