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question about JESD204B subclass1 mode

inhwan kim
Prodigy 145 points
Other Parts Discussed in Thread: LMK04828

Hi

I have a question about JESD204B subclass1 mode.

As I know, subclass1 mode uses sync for alignment, and subclass2 modes uses sysref for the data alignment.

what if my JESD204B uses sub-class1 mode,
do I need to care about sysref still?
Can I just focus on sync signal to align data?

I used AND gate for two sync_1 & sync_2 as below captured image

the following capture image is the data in RX side (using chip scope)

This test uses sine function as an input.

As you see, data looks not aligned (also sysref is not aligned)

I am just curious about that

can I just ignore "sysref" which is not aligned for data alignment, since i have used subclass1 mode.

what if i have three different AD board & each AD board has LMK04828 as below image

if sync is high (output of AND gate from first image), is it possible to have delay(for data) between AD_0 & AD_1?

when I checked the data with chipscope, there was around 20 sample difference between two different port (different board)

Can I assume that sync is not aligned?

if I can see two sync signal is high and the input "sync" into ADC is high,

then Can I just say that it is aligned?

I am so confused because of the delay between ADC data channel.

I will appreciate any comment or help

Thank you

  • 0
    TI__Mastermind 28550 points

    Subclass 1 requires SYSREF for deterministic alignment of logic devices and converter devices.

    See figure 36 of JESD204B specification.  While SYNC~ is asserted to a TX device, it transmits K frames.

    The purpose of the SYSREF in Subclass 1 is to ensure the LMFCs all have a deterministic timing relationship.

    What ADC are you using at what device clock frequency?  If low frequency then perhaps subclass 2 can be used where the phase of LMFC is set by rising edge of SYNC~ (see JESD204B spec  section 4.8)

    73,

    Timothy