• State Resolved
  • Locked Locked
  • Replies 3 replies
  • Answers 1 answer
  • Subscribers 21 subscribers
  • Views 371 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Why the phase difference between input_ref_clk and output_clk is random when the CDCM6208 is locked?

wangzhi
Prodigy 150 points
Other Parts Discussed in Thread: CDCM6208, LMK04906, LMK04828

I use CDCM6208 on my board.

When I measure the phase difference between input_ref_clk(25MHz, from  a crystal) and output_clk(100MHz), I found that the phase difference is always random when I powered on the board every time.

In my understand, the PLL should make the phase of output_clk equal to the input_ref_clk, so that is Phase Lock Loop!

But why the phase difference is not the same value when I power on the board every time?

  • 0
    TI__Genius 10320 points
    Hi Zhi,

    The CDCM6208 does not feature a 0-delay feature (unlike the LMK04906 or say LMK04828/LMK0480x families) which allows for a guarantee between input and output phase alignment. Dividers internal to the device can create possible valid phases for lock - these are not deterministically aligned to the input after device reconfiguration.

    If you want 0-delay functionality, please reference the devices I mentioned above.

    Gabe
  • 0 in reply to Gabe Ayala
    Prodigy 150 points

    Hi Gabe,

    Thanks for your reply.

    With your mentioned, I think that:

    1. the internal output divider make random phase difference. Is it right?

    2.There is NO phase difference between the VCO output and the input clk in the CDCM6208.  Is it right?

    3.If the feedback path is from output divider to the input of PFD in the CDCM6208, it should be 0-delay phase. Is it right?

  • 0 in reply to wangzhi
    TI__Genius 10320 points

    Hi Zhi,

    1) when dividing by N, there are N possible phase relationships which are valid (phase relationship is not random, just which one is "selected" is not deterministic)

    2) there is internal delay, but if no divider is being used, this is deterministic

    3) because the feedback path has 2 dividing stages (prescalar and feedback divider), there could be  PS_A + FEEDBACK possible phases which the PLL feedback path is referencing. Because we cannot guarantee which feedback phase is being referenced (unlike in 0-delay complaint devices where this relationship is deterministic), the CDCM6208 is not guaranteed to have a known phase relationship between input and output. 


    Gabe