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LMK01801 sync btw Bank A and Bank B

user290816
Prodigy 40 points
Other Parts Discussed in Thread: LMK01801

Hi,

I meet a problem to sync lmk01801 bank A & B.

Here is the setting:

uWire control and automatic sync, sync_en_auto =1 and program Register R5,  Lvpecl and divide by 2.

Clkin0 and clkin1 are both 400MHz and synchronized. 

I expect to have clkout0 to clkout11 synchronized 200MHz, within the bank there is no problem,  but sometimes after power up, 180 out of phase can be observed btw bank A and B, how can I solve this? 

Thanks

Jason

  • 0
    TI__Genius 10320 points
    Hi Jason,

    Just to clarify, do you see this phase shift after power up (via Register writes or power cycle?) and before programming anything to R5? Or does this phase shift occur after power up, register write to R5, and then sometimes there is a 180 degree phase shift?

    Thanks for the clarification,

    Gabe
  • 0 in reply to Gabe Ayala
    Prodigy 40 points
    after power up, FPGA will write the register automatically, so this is observed after power up and register writing.
  • 0
    Prodigy 40 points
    Command Sent to LMK01801


    0x48003210
    Reset Register (R0)

    0x48003200
    Recover From Reset (R0)

    0x22224921
    Set Clock Output Type (CH7~0)

    0x02222222
    Set Clock Output Type (CH13~8)

    0x1630C003
    Auto Sync.

    0x00000925
    CH 13~0 Clock Divide by 2





    --------------------------------------------------------------------------------
  • 0 in reply to Gabe Ayala
    Prodigy 40 points
    Gabe,We are really in trouble.
    When the clocks are 180 out of sync, the sync command can make them aligned; BUT repeating the sync command, it's possible that the clocks are out of sync again, with 180 degree phase shift.
  • 0 in reply to user290816
    TI__Genius 10320 points

    Hi Jason,

    The timing diagram in the LMK01801 DS is representative of the internal timing of SYNC per Bank. Although reference clock alignment can help mitigate the effects that you are seeing, the split nature of the LMK01801 can not deterministically provide guaranteed sync between banks, but can inside a bank (as you have observed). Because of internal propagation delay variation between banks, SYNC events could generate 2 possible phases 0° or 180° (in the /2 case, for example a /4 case would allow for misalignment between banks of 0°, 90°, 180°, or 270°).

    Gabe