Dual LMK04828

Jon Reyland

Other Parts Discussed in Thread: LMK04828, DAC37J84

Hello Clock Expert:

I have two DAC37J84 Eval cards connected to two FMC connectors on a Xilinx VC707 FPGA Eval card. Using the TI DAC setup GUI, I setup both eval cards with external clock and drove both with a 983.04 MHz clock, no problem.

My JESD Verilog program has a JESD204 phy layer driver for each DAC37J84 Eval card, those also work well.

The problem is synchronizing SysRef to each of the two DACs. I generated a 800 nsec. pulse, and sent it to pin 6 SYNC input of each LMK04848 clock cleaner chip (one on each eval card), However I can't figure out what to set the LMK SysRef Mux and Sync modes to. Would you please recomend the LMK setups I need? I really appreciate your help.

Thanks,

John Reyland

I can send you screen shots of all my DAC and LMK setups if that helps

over 10 years ago

0 Julian Hagedorn over 10 years ago

TI__Mastermind 20900 points

Hello John

we are working on the answer.
Do you have matched trace length for the pulse from FPGA to LMK04828?
What SYSREF/DeviceCLK frequency do you use for the DACs?

best regards,
Julian

0 John Reyland62 over 10 years ago in reply to Julian Hagedorn

Intellectual 375 points

I am using two DAC37J84 eval cards, the cables from the FPGA card to pin 6 of the LMKs on each eval card are matched .

Also, the pair of DACs (one on each eval card) each have LMFS = 8411. Also, K = 20 (see attached setup screens). The 32 byte multiframe rate is 245.76 MHz and the DACCLK = 983.04 Mhz = sampling rate. I think is 245.76 MHz is the max SysRef. However since K=20 SysRef = 245.76/20 ? I am not entirely sure.

Please advise,
John Reyland

Clock & timing

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Dual LMK04828