Other Parts Discussed in Thread: LMK03806
Hello
In the LMK03806 datasheet it states in comment 1) at page 7 that for best low jitter results one should use a LVPECL/ LVDS clock input due to their good slew rate.
However, the OSCin connectivity figures (Fig 11-13) don't specify how to connect a LVPECL signal to the LMK.
In case I have a differential LVPECL XO which I want to connect as the clock source to the LMK03806 OSCin/ OSCin* pins,
and assume I connect the XO outputs to 200ohm pull down resistors, and couple them with 100nF capacitors, how do I continue the design?
Direct "clean" connection to OSCin/ OSCin* pins?
Add 51ohm termination as in Fig 12/ 13?
Can you please add a sketch of the suggested connectivity between the LVPECL XO and the LMK03806??
May I suggest you add such a figure to your datasheet...
Thanks
Amnon
