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Is this possible to use CDCE62005 configuration?

Other Parts Discussed in Thread: CDCE62005, LMK03328, CDCM6208, CDCE62005EVM

 

Two reference frequency components Pri_frq and Sec-frq are used and

Output 1, Output 2 are generated using Pri_frq and Output 3 is generated using Sec_frq.

Is it possible this way to generate multiple clock sources which are created by two independent references simultaneously?

More specifically, Pri_frq will be fixed as constant, on the other hand Sec_frq will be persistently changed. Output 1 and Output 2 will be fixed and

Output 3 which is generated based on Sec_frq, will be changed as Sec_frq is changed.

Does CDCE62005 have this function?

 

I am looking forward for your replies.

Thank you.

 

  • Hello Jang,

    CDCE62005 does have a single PLL only. With this architecture it is not possible to achieve the frequency plan.

    There are 2 options available:
    1. The newly released LMK03328 does have 2 PLL which can be configured to generate the requested frequencies.
    2. In case the 40MHz does not need to be phase locked to the 20MHz. a single PLL with fractional output divider could help. If the jitter/phase noise requirement on 40MHz is relaxed then the CDCM6208 could be an option.

    best regards,
    Julian
  • Thanks Julian.

    I can understand due to your kindness reply.

    May I ask one more?

    I'm using CDCE62005EVM.

    Whenever CDCE62005 output is turned on, it gets hot as more than 70 degrees celcius.

    I think this is a serious problem, is there a way to solve this problem?

    Do all other Clock generators heats up like this?

    If they don't can you recommend other Clock generater model that is heatless? 

     

    Best regards.

    Jang Eun Ki

  • Hello Jang,

    sorry for the late answer.

    CDCE62005 is a power hungry device and heats up therefore.
    The follow on device is the CDCM6208 with lower power and better performance.

    best regards,
    Julian