LMK04828 PLL1 + PLL2 lock OK but sometimes, some clocks are missing at the output

Hello gjoli,
can you please clarify about your your full device configuration as well as your input reference which you try to jitter clean and the VCXO you are using.
Please also share the passive loop filter components you used in PLL1 & PLL2.
Did you design your own PCB already or do you use the TI EVM?

Thanks!

Best regards,
Patrick

Hi Patrick,

We designed our own PCB based on the ADS42JB49 EVM schematic.

We are using an unipolar 10MHz ref clock connected to the CLKIN1 input.

The VCXO is a CVHD-950-100.000

The PLL2 is running at 2400MHz in order to generate only 200MHz LVDS outputs

The passive loop filter is the following :

We believe the PLL is properly locked, just some output which are missing.

Here is the full config :

#############################
# Reset the LMK, enable the 3-wire management
W 00000000 80
# Ensure the LMK is not in a power-down state
W 00000002 00
#############################
W 00000000 00
W 00000002 00
W 00000100 0C
W 00000101 55
W 00000102 55
W 00000103 00
W 00000104 20
W 00000105 00
W 00000106 70
W 00000107 11
W 00000108 0C
W 00000109 55
W 0000010B 00
W 0000010C 20
W 0000010D 01
W 0000010E 70
W 0000010F 11
W 00000110 0C
W 00000111 55
W 00000113 00
W 00000114 20
W 00000115 00
W 00000116 70
W 00000117 11
W 00000118 0C
W 00000119 55
W 0000011B 00
W 0000011C 20
W 0000011D 00
W 0000011E 70
W 0000011F 11
W 00000120 0C
W 00000121 55
W 00000123 00
W 00000124 20
W 00000125 00
W 00000126 70
W 00000127 11
W 00000128 0C
W 00000129 55
W 0000012B 00
W 0000012C 20
W 0000012D 00
W 0000012E 70
W 0000012F 01
W 00000130 0C
W 00000131 55
W 00000133 00
W 00000134 20
W 00000135 00
W 00000136 70
W 00000137 00
W 00000138 07
W 00000139 00
W 0000013A 00
W 0000013B 18
W 0000013C 00
W 0000013D 08
W 0000013E 00
W 0000013F 00
W 00000140 04
W 00000141 00
W 00000142 01
W 00000143 00
W 00000144 00
W 00000145 7F
#############
# CLKIN1
W 00000146 12
W 00000147 1B
#############
W 00000148 0C
W 00000149 0C
W 0000014A 02
W 0000014B 16
W 0000014C 00
W 0000014D 00
W 0000014E C0
W 0000014F 7F
W 00000150 02
W 00000151 02
W 00000152 00
W 00000153 00
W 00000154 0a
W 00000155 00
W 00000156 0a
W 00000157 00
W 00000158 0a
W 00000159 00
W 0000015A 64
W 0000015B D4
W 0000015C 00
W 0000015D FF
W 0000015E 00
W 0000015F 0B
W 00000160 00
W 00000161 18
W 00000162 04
W 00000163 00
W 00000164 00
W 00000165 48
W 0000017C 15
W 0000017D 33
W 00000166 00
W 00000167 00
W 00000168 48
W 00000169 59
W 0000016A 08
W 0000016B 00
W 0000016C 00
W 0000016D 00
W 0000016E 13
W 00000173 00
W 00001FFD 00
W 00001FFE 00
W 00001FFF 53

Thank you for your help.

BR

Hello gjoli,

I will crosscheck your config. Can you please also let me know your power supply connections? Did you mimic the ADS EVM?

Is the glitch happening on outputs sharing a common power supply or receiver?

When you prefer to share data in the forum, please check my profile for contact data.

Best regards,

Patrick

Hi Patrick,

I sent you the schematic by PM.

We often see the issue on DCLKout10 while DCLKout8 is correct, so, same VCC_CG.
But sometimes it was the opposite, we see a clock on DCLKout10 while nothing on DCLKout8.

BR

Hello gjoli,
I checked the configuration.
Can you please insert the following from our recommended sequence?

[...]
W 00000165 48
### TI recommended sequence ###
W 00000171 AA
W 00000172 02
W 00000173 00
### TI recommended sequence ###
W 0000017C 15
[...]

Apart from above recommendation, everything is configured alright. I also checked the PLL design. It looks ok so far.

I would recommend to check if the input signal looks ok at the device pin. I'm unsure whether you can measure at OSCout when I look at your schematic.
Please try to use the status pins to check whether the CLKin1 and the OSCin signals look to be stable at the PLL1 and PLL2.
--> 0x0157 & 0x016E

Best regards,
Patrick

Hi Patrick,

Thank you for your feedback.

We checked the LOS of PLL1 and PLL2 and both PLL are always stable.

Regarding the programming sequence, we followed the datasheet recommendation but we just noticed it has been updated in december with :

9.5.1 Recommended Programming Sequence
Registers are programmed in numeric order with 0x000 being the first and 0x1FFF being the last register
programmed. The recommended programming sequence from POR involves:
1. Program register 0x000 with RESET = 1.
2. Program registers in numeric order from 0x000 to 0x165. Ensure the following register is programmed as
follows:
– 0x145 = 127 (0x7F)
3. Program register 0x171 to 0xAA and 0x172 to 0x02.
4. If using LMK04821, program register 0x174.
5. Program registers 0x17C and 0x17D as required by OPT_REG_1 and OPT_REG_2.
6. Program registers 0x166 to 0x1FFF.
When using LMK04821: Program register 0x174, bits 4:0 (VCO1_DIV) with proper value before programming
PLL2_N register in 0x166, 0x167, and 0x168 for proper total PLL2_N value.
Program register 0x171, 0x172, 0x17C (OPT_REG_1) and 0x17D (OPT_REG_2) before programming PLL2 in
registers: 0x166, 0x167, and 0x168 to optimize PLL2_N and VCO1 phase noise performance over temperature.

Can you confirm this is the actual recommendation to follow ?

0x173 is not part of the recommended sequence

Thank you

Hello gjoli,

the 0x173 is part of step 6.

Sorry, I was not referring to the LOS signal, but to the PFD signals which can be routed to the status pins for observation.

This way you can observe the input reference and the output of a PLL at the same time and judge where the issue is happening.

When you can observe that the PLLs stay clean and the glitch is only happening on a specific output pair:

From your schematic I think that the outputs of question might have a different type of receiver?

Can you please try if there is an impact from this receiver?

All the output pairs are configured in similar fashion. I would expect that they behave all similarly.

Can you please check the power connection of the output pair?

Best regards,

Patrick