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LMK04803: Fixed Digital delay

toshi-e2e
Genius 4830 points
Other Parts Discussed in Thread: LMK04803, CODELOADER

Hi all,
My customer has evaluated LMK04803, and  tried to adjust delay digitally by using SYNC signal.
The result was about 11.84ns against the expectation value, (VCO 1843.2MHz) x (6 + 5)=5.967ns
Could you please give me your advice for solving this?

The setting are as follows;
 
 Manual SYNC input
 OSCin=30.72MHz
 CLKoutX_Y_DDLY=5cycle
 CLKoutX_Y_HS=Normal
 ADLY=Bypass
 VCO_MUX=VCO Select
 VCO frequency = 1843.2MHz

The .mac file for Codeloader is attached. Please change the extention from .txt to .mac.
 

Fullscreen lmk04803.txt Download 
[SETUP]
ADDRESS=888
CLOCK=4
DATA=2
LE=6
PART=LMK04803B
PINPOSITION00=1
PINPOSITION01=7
PINPOSITION02=5
PINPOSITION03=10
[MODES]
NAME00=R0 (INIT)
VALUE00=131072
NAME01=R0
VALUE01=192
NAME02=R1
VALUE02=481
NAME03=R2
VALUE03=2147484034
NAME04=R3
VALUE04=2147483779
NAME05=R4
VALUE05=388
NAME06=R5
VALUE06=2147483653
NAME07=R6
VALUE07=16842758
NAME08=R7
VALUE08=285278215
NAME09=R8
VALUE09=65544
NAME10=R9
VALUE10=1431655753
NAME11=R10
VALUE11=2516599562
NAME12=R11
VALUE12=890245131
NAME13=R12
VALUE13=319553644
NAME14=R13
VALUE14=319021325
NAME15=R14
VALUE15=33554446
NAME16=R15
VALUE16=15
NAME17=R16
VALUE17=3243574288
NAME18=R24
VALUE18=24
NAME19=R25
VALUE19=46777337
NAME20=R26
VALUE20=2410151962
NAME21=R27
VALUE21=268436155
NAME22=R28
VALUE22=4194332
NAME23=R29
VALUE23=8389917
NAME24=R30
VALUE24=100664606
NAME25=R31
VALUE25=63
OSCIN00=30.72
EXTRA_PLL_N_DIV_1_00=1
OSCIN01=30.72
EXTRA_PLL_N_DIV_1_01=1
PINS=1
[BURST]
COUNT=0
[FLEXHASH]
HASHVALUE=0

Regards,
Toshi

  • 0
    TI__Mastermind 28550 points
    Is the customer measuring from rising edge of LVCMOS to rising edge of output?

    Can you advise what the rise-time (20 to 80%) of the LVCMOS signal used for SYNC is?

    If you program another output to have a DDLY of 6 cycles, it results in 1 VCO cycle difference? 542.53 ps.

    The timing for the capture of the SYNC signal for the input is not defined.

    73,
    Timothy
  • 0 in reply to Timothy T
    Genius 4830 points

    Timothy-san, thanks for your support.

    The following is my answer.

    Is the customer measuring from rising edge of LVCMOS to rising edge of output?

    ->  No, from falling  edge of LVCMOS to rising edge of output because of SYNC_POL_INV = 0.

    Can you advise what the rise-time (20 to 80%) of the LVCMOS signal used for SYNC is?

    -> The fall-time is about 600ps.

    If you program another output to have a DDLY of 6 cycles, it results in 1 VCO cycle difference? 542.53 ps.

      ->  I will ask my customer to check it.

    The timing for the capture of the SYNC signal for the input is not defined.

      -> Below is the captured waveform.
     　　CH1 (Blue) is SYNC at SYNC PIN and CH4 (Green) is OUTPUT at FPGA input, (not CLKout pin). 
          The timing from SYNC pin to  CLKout pin is 11.84ns.
          The distance from CLKout pin to FPGA input is about 150mm.

    Thanks and regards,
    Toshi

  • 0 in reply to toshi-e2e
    Genius 4830 points
    Timothy-san,
    I confirmed to my customer that when the output was programmed a DDLY of 6 cycles, it resulted in 1 VCO cycle difference, 542.53 ps.

    Regards,
    Toshi
  • 0 in reply to toshi-e2e
    Genius 4830 points
    Hi,
    Could you inform me of the present situation?

    Regards,
    Toshi
  • 0 in reply to toshi-e2e
    TI__Mastermind 28550 points
    I think at this point, I'm going to need to test the configuration in the lab. I'm going to see what the schedule is like. By what date do you need input?
  • 0 in reply to Timothy T
    Genius 4830 points
    Timothy-san,
    Thanks a lot for your support.
    My customer would like to receive the results as soon as possible.
    But, I can negotiate with my customer.
    Could you please tell me your plan?

    Thanks and regards,
    Toshi
  • 0 in reply to toshi-e2e
    TI__Mastermind 28550 points

    Plan is to...

    • test settings you sent prior on eval board to see if we can identify any reason for not getting same results as per datasheet.
    • If we replicate customer result and not datasheet will interact with designer to see reason for discrepancy with part vs. datasheet.
    • Provide update.

    73,

    Timothy

  • 0 in reply to Timothy T
    Genius 4830 points
    Hi, Timothy-san,
    Thanks for your response and support.
    I am looking forward to receiving the result.

    Regards,
    Toshi
  • 0 in reply to toshi-e2e
    TI__Mastermind 28550 points

    Hello Toshi-san,

    We investigated the today and found that there is an approximate 6 ns propagation delay from the SYNC pin to the SYNC trace seen in figure 11.  From the datasheet on page 33 is the comment about the SYNC pin being a CMOS input.

    Note: Due to the speed of the clock distribution path (as fast as ~325 ps period) and the slow slew rate of the
    SYNC, the exact VCO cycle at which the SYNC is asserted or unasserted by the SYNC is undefined. The timing
    diagrams show a sharp transition of the SYNC to clarify functionality.

    As such, over many devices, temperature, voltage, you may find a small variation of SYNC to clock start time of +/- 1(?) VCO cycle.

    Further, we observed that changing the amplitude of the SYNC signal/slew rate could vary the propagation time.

    If timing from a SYNC signal to output clock is critical, I suggest considering LMK0482x family which has the ability to use CLKin0 as a differential high speed SYNC signal to the dividers.

    73,

    Timothy

  • 0 in reply to Timothy T
    Genius 4830 points
    Hi Timothy-san,
    Thanks for your answer.

    I need to understand more.
    You mentioned that there is an approximate 6 ns propagation delay from the SYNC pin to the SYNC trace seen in figure 11.
    Is the 6ns delay from Sync pin to SYNC trace an additional delay?
    Is the customer's result correct?

    Regards,
    Toshi
  • 0 in reply to toshi-e2e
    TI__Mastermind 28550 points

    Hello Toshi-san,

    Yes, the customer's plot is correct.  The figure 11 is from the digital in the chip perspective.  As measured, before the SYNC signal arrives, there is some propagation delay from the gate.

    And also important is if precise timing is required from SYNC, it is not assured due to variation in that propagation delay and because it is re-clocked, a small analog shift in propagation delay could result in the output skipping an entire vco clock period (or clock distribution period, which is vco clock period after VCO divider, if VCO divider used).

    73,

    Timothy