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LMK04828 : SYNC_DISSYSREF Bit setting question

Other Parts Discussed in Thread: LMK04828, CODELOADER

I have another problem with the LMK04828.

There is a control called “SYNC_DISSYSREF” located at bit 7, register 0x144.

I cannot not set that bit to logic 1. It always resets itself back to 0.

 

I am controlling that bit as part of the calibration sequence given in the data sheet pages 37-38 (see steps 2 and 3), but it doesn’t matter because I have not been able to set it under any condition.

In the procedure register 0x144 must be set to x00 during the clock alignment cal, and then set back to xFF to avoid an unintentional cal.

 

If I write data = xFF, the register reads back x00

If I write data= x80, it returns x00

If I write data x7F, it returns x7F

 

So not only doesn’t bit 7 set, when forced high it causes the other 6 bits to reset to 0.

If the device is powered on, and I write only to this register the bit still cannot be controlled. I have not found a configuration that allows bit 7 to be set.

I have also tried this on multiple devices with the same results.

 

Can you  give some guidance as to what is wrong?

  • I presume this is on your own PCB with your own software vs. CodeLoader + EVM?

    Can you send a waveform of the SPI write to 0x144 with 0xff and 0x7f?


    -

    The only other things I can think which could trip you up is...

    • if the device is getting RESET to POR values?  You may consider setting the RESET pin as output.
    • if the SPI lock is getting set and the write isn't taking.
    • Are you sure your read back is working correctly in your software?
      • Can you send the SPI waveform of the SPI read with 0x144 as 0xff and 0x7f?

    73,

    Timothy

  • This is an oem board and software.
    There are 4 LMK04828 devices on the board (as well as 5 other SPI devices). There is no problem with read/write to any other registers in the LMK or any of the other devices (over 1000 registers), so the SPI interface is solid. And as stated below I can control to the lower 6 bits of register 0x144 without a problem.
    SPI lock registers are set to 0,0 0x53.

    It doesn’t seem a likely fix, but I will instantiate the RESET and try again.

    Are there other register settings within the LMK04828 that could affect the behavior of the SYNC_DISSYSREF signal?