• State
  • Locked Locked
  • Replies 2 replies
  • Subscribers 21 subscribers
  • Views 691 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

LMX2592 web tool

JohnP
Intellectual 470 points

Other Parts Discussed in Thread: LMX2592

Hi All

When will there be a web tool to simulate the performance of the LMX2592? What will the spur levels be with output frequencies from 4.4GHz to 8.4GHz with minimum step size? How do you design for maximum output power over the same bandwidth, the datasheet section 8.1.6 does not clarify the "characteristic " capacitance?

Thanks

JP

  • 0
    TI__Mastermind 28031 points

    JP,

    Currently, the clock architect can be used to simulate performance on these devices.  We recently added a spur simulation.

    We are also planning to release a new software in about a month that will give a more detailed simulation, but this is not ready yet.

    Regards,

    Dean

  • 0 in reply to Dean Banerjee
    Intellectual 470 points

    Hi Dean

    Thanks for taking the time to reply. I had tried to use the tool to generate simulations but found it didn't cooperate. However now if I reduce my frequency range to that of the doubled output, it does! Makes sense really.

    Please can you make the tool simulate effects of using the various input dividers and multipliers, especially in terms of phase noise and spurs? That is, so that the user can avoid spurs by varying the phase detector frequency.

    Please can you also suggest how to maximise the output power over the 4.3 to 8.3GHz range and explain the  "(characteristic)" capacitance in section 8.1.6 in the data sheet?

    Thanks

    John