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SN74SSQEC32882 Layout Questions

Richard Elmquist
Mastermind 45250 points

I do not have access to the data sheet for these parts so I am asking the following question from one of our sales reps:

Do the SN74SSQEB32882ZALR and SN74SSQEC32882ZALR require any external routing or parts on the feedback pins?

Is there any design collateral that would show this for this part? Can you send me a complete data sheet for reference? My email is richardelmquist@ti.com.

Sorry to ask this type question in the forum, but I cannot find anything to help me answer this question.

Thanks for your help with this!

Richard Elmquist

  • 0
    TI__Mastermind 45250 points

    Has anyone had a chance to look at the request above?

    Thanks for your help with this!

    Richard Elmquist

  • 0 in reply to Richard Elmquist
    TI__Mastermind 24205 points

    Hi Richard,

    I have forwarded the query to the applications engineer responsible for this device. Someone will get back to you shortly.

    Regards

    Arvind Sridhar

  • 0 in reply to Arvind Sridhar
    TI__Expert 5325 points

    Hello Richard,

    the DDR3 register devices are compliant to the JEDEC SSTE32882 standard. JEDEC members (=registered for free on the website) can download the spec at JEDEC. We provide our data sheet upon direct customer request under "TI Information - Selective Disclosure" (to handle similarly as JEDEC with registration in the community).

    The part is meant to be used in standardized DDR3 RDIMMs. The layout, matching and passives are all standardized and agreed upon by JEDEC members. It is the individual designer responsibility to create a spec conform environment for the part.

    To quickly summarize the most important points:

    The data sheet contains a (mandatory) power supply filter for the PLL domain.

    The clock input is terminated using 120Ohms differential.

    Trace impedance of the input and output signals is 60 Ohm single ended. The reference plane is VDD, not VSS. Output signals are terminated at the end of the fly-by using resistive termination to VTT=VDD/2. The resistor value depends on signal integrity of the respective fly-by topology. (often 30..40Ohm range) VTT is decoupled to VDD.

    The external feedback loop exists only for legacy purposes in case someone would populate a 1st generation device (SSTE32882). The later generations like SSQEB32882 and SSQEC32882 use an internal feedback loop path.

    I may add here that a customer has to check if the memory controller IP they use is compatible to the registered standard. There are differences in timing and protocol (and register start-up sequence). They cannot just plug it to "any DDR3 FPGA".

    Please let me know when you would like to have the full data sheet. I will send it to you by e-mail.

    Best regards,

    Patrick