CDCM7005-SP Evaluation Board

Hello Kamdin,
by default the dividers are set for 61.44MHz reference and the VCXO for 491.52MHz, so you should be fine with just applying power.
The Y outputs should show 61.44MHz divided from the VCXO. Please confirm that J24 is open as well.
Can you please let me know which signal generator you have and how much swing you apply?

Thanks!

Best regards,
Patrick

Hi Patrick,

Thanks for the replay. J24 is open.
I even programmed the Y0 to be LVCMOS. Word 2 as DB6D 94A2.
It is 61.44Mhz.
I connected the Y0 output to the PRI_Ref.
So the reference clock is in phase with VCXO. (can not get better than this).

I still don't see any pulses at the TP1 and D3 (PLL_Lock) is not on.

The signal at J5-2 is not quite at the LVCMOS because of source resistors. But I would expect to still see something? like on and off of pll lock.

Please advise.

Thanks,
Kamdin

Kamdin,
What frequency is the reference clock that you are providing?
How accurate is this frequency? Can you vary it by +/- 5 or 10khz and look for lock around 61.44Mhz.
I believe that the 491.52Mhz VCOs are not as precise as prior versions and have shorter pull range.
I am not sure if feeding back the Y0 to reference will work, as any phase adjusts will affect Y0 as well. I do not think it will be stable and lock.
Regards,
Wade

The frequency is 61.4Mhz.

I can only change it by 100Khz increments.

What I don't understand is why there is no pulses at the CP output. even if it is not locking, I should see pulses.

The CP is always low. I can set it to Vcc/2 by programming it. so that means it is not tri-state.

I have another board that we have a 160Mhz VCXO on it and I am applying the 20 MHz at the PRI_REF. It behaves the same way. doesn't matter how much I vary the reference clock.

It has puzzled me that no matter what I do I can not get CP output to change.

Is there any way (i.e., test mode) I can bring some internal signals out to see what is the issue?

Thanks,

Kamdin

Kamdin,

I just reviewed the our EVM test plan information.

It indicates a lock should occur with default conditions within +/-10kHz of 61.44Mhz.   Thus, your resolution of frequency may not be enough to insure lock.

The CP output should be high when ref clock frequency is above 1/8 of VCXO frequency, and low when lower then 1/8 of VCXO frequency.

I am pulling my boards out of storage after a move, and will set up to confirm above.

Can you verify with more precise ref clock source?

Regards,

Wade

Hi Wade,

Thanks for you response.

Exactly as you mentioned, I was expecting the CP output to go low and high as I am changing the PRI_REF frequency.
But the output does not change and always low.
So what am I missing? or doing wrong?

The PRI_REF clock source is a function generator. I have adjusted the output so the signal at J5-2 is LVCMOS.
I can change the frequency in the increment of 100KHz.
But again I want to see something at the output of CP. Nothing. It is always low.


Thanks,
kamdin

Kamdin, I apologize for delay.
I do have my boards now, but my clock source is in cal. They promised it would be complete Monday.
If it is not, I will scavenge another clock source.
I do think 100kHz is too large of adjustment range.
I will post back Monday with results of my test.
Regards,
Wade

Hi Wade,

Thanks.

So why the CP out does not changes for me when I change the ref frequency to below 1/8 of VCXO or above it?

The output is always zero?

Also, shouldn't I be seeing pulses that changes width when I put a scope on the CP out pin as I change the frequency of ref clock?

In my case it is always low?

Thanks,

Kamdin

Kamdin,
I was measuring the V_CTRL node, not the CP_OUT.
Though the behavior I noted should result in different duty cycles on CP_OUT. I simply used DC meter to probe the V_CTRL net.

Try measuring on V_CTRL. I am not sure what the voltage signal on CP_OUT would look like under each case.
Regards,
Wade

Wade,

V_CTRL and CP_OUT are the same voltage level. The Eval board is set up to have passive feedback as default.
I see the same low level on V_CTRL and CP_OUT for all conditions.
Also when you change the direction of the charge pump current, I see the reverse of the behavior, where the output voltage changes from high to low as I change the ref frequency from low (<1/8 freq of VCXO) to high.

Is there anyway I can look into the internal signals at the charge pump (maybe by putting it in some sort of test mode?)
or is there another parameter that I can change to have the CP_OUT change so at least get i some responses from the chip and then I can play with the parameters?

Thanks,
kamdin

Kamdin,
I just pulled the specification for the VCXO on the EVM.
It is specified as a +/-50ppm pull range. This will allow it to adjust by +/- 24.57khz
This divided by 8 will be only 3khz range for locking.

One option that you can try would be to reduce the divider to increase the effective pull range to the ref clock.
Practically speaking, you will only be able to divide by 4, as divide by 2 will exceed ref clock input max frequency of 200MHz.

I strongly suggest that you attempt to try to lock with a ref clock that has finer degree of resolution to match the pull range of the VCXO.

You may be able to achieve lock with a divide by 4, and setting the ref clock to 122.88MHz. This is close to the center of the target frequency. Though, it is uncertain how accurate your clock source is.

To my knowledge, there are not any test modes available to user that would be beneficial in diagnosing issue.

I do not know why you are not seeing the V_CTRL going high and low. Unless, it is far enough away that it cannot determine correct phase to adjust to.

Regards,
Wade

Thanks.

I am not sure why my system does not behave the same way.

Can you do another test on your system so I can compare it to my system?

If you program one of the outputs to be LVCMOS, and connect that output to PRI_REF clock then you should have a divide by 8 that is in the center of frequency.

Does the system locks in this case?

Thanks,

Kamdin

Kamdin,
I don't think it will be stable when attempting to lock onto its own signal.
I was going to test this, but am encountering hardware issues. We recently moved into new lab, and much of the old "seemingly" usesless hardware was scrapped. Thus my adapters to do this are no longer.
I have searched for them, and have to just order new. I will attempt to test the self feedback as soon as hardware shows up.
I do not expect it to lock though.
Regards,
Wade