CDCLVP1204 Drive Strength

Jason Fan

Other Parts Discussed in Thread: CDCLVP1204

Hi , Experts. My customers called T&W electronics is designing the layout of the CDCLVP1204 part in the 5G PON. The challenge is the trace from the CDCLVP1204

to the receiver is about 5000mil in FR4 board and the impedance is around 100. The signal is the 156.25Mhz clock . So they concern the trace is too long for our

buffer driving. Could you please input your comments , thanks!

over 10 years ago

0 Alan O over 10 years ago

TI__Mastermind 32575 points

CDCLVP1204 has fast edge rate (<200 ps rise/fall time, 20%-80% levels) so it can drive 5-inch, 100-ohm differential pair on FR4 board. What is the receiver's minimum differential pk-pk input swing and maximum rise/fall time requirement?

They can use the CDCLVPxxxx LVPECL driver model in the IBIS file to simulate the signal integrity with their PCB and receiver models.

Here's the link to the IBIS file: