Other Parts Discussed in Thread: CDCE706, CDCE937, CDCE925, CDCE913, CDCE949, CDCE906
I have a CDCE706 that provides the core clock frequency to the processor. Can I reprogram the PLL chip to provide a new frequency to the processor without causing glitches, etc that would cause undesired behavior (assuming, I program it correctly)?
The CDCE706 allows changing programmatically the output frequency via I2C, but to change from Frequency1 to Frequency2 avoiding intermediate frequencies or glitches, is not as straight forward as using the CDCE925, CDCE937, CDCE949, CDCE913.
If in order to change from Frequency1 to Frequency2 only one PLL parameter (N or M) needs to change. For example, if in high speed mode with a clock input of 25MHz, changing from 300MHz to 180MHz can be done with different N, M PLL configurations. If choosing for 300MHz a setup of N=12 and M=1 and then to program the CDCE706 to 180MHz with (N=72 and M=10), as N or M are not sharing the same register address, one of them would be updated first, therefore if I chose writing first M=10, I will get an intermediate frequency of 30MHz, before I write N=72 getting the final 180MHz. That is not a concern for the CDCE925, CDCE913, CDCE937, CDCE949) where there is a bit that selects the PLL settings active, therefore the PLL setting inactive can be written and once that is completed use that bit to activate it. More details are included in the Application Note: http://focus.ti.com/general/docs/lit/getliterature.tsp?literatureNumber=scaa105&fileType=pdf
Changing from 300MHz to 180MHz can be done without intermediate frequencies or glitches looking by taking into account to only change one PLL parameter (N or M) to go from frequency1 to frequency 2. If the PLL parameters for 300MHz are chosen to be (M=10 and N=120), then programming the PLL to M=10 and N=72, only implies N to change and therefore a smooth change in terms of period and duty cycle as can be seen in the plot below can be seen, in a lock time of 25.7us.
In the plots below, note that the the pink graph is the frequency, the yellow is the period and the blue is the duty cycle of Y0 when reprogrammed to go from PLL settings 1 to PLL settings 2, in order as explained above.
The lock time for the CDCE706 and CDCE906 varies with the delta of the change but the worst case for each of the increases of decreases is as follows:
-in high speed mode when going from 180MHz to 300MHz is 3.5us.
-in normal mode when going from 200MHz to 80MHz is 40us
-in normal mode when going from 80MHz to 200MHz is 9.3us
If changing the frequency without caring about intermediate frequencies I would recommend using the CDCE925, CDCE913, CDCE949 or CDCE937, they are the same type of device with some added functionality, please note that the core supply for them is 1.8V, although the output stage can be powered also a 3.3V and 2.5V, therefore they support also a 3.3V or 2.5 LVCMOS too.
