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LMK04828 PLL1 does not lock

Other Parts Discussed in Thread: LMK04828

Good morning, I am using a LMK04828 evaluation board (EVM) and I want to generate some clocks from a base clock at input CLK1 of 1.159245 MHz.

These are the settings:

CLK1 = 1.15924 MHz

PLL1 R counter = 2 

PFD frequency = 579.6225 kHz

PLL1 N counter = 212

VCXO frequency = 122.88 MHz

CP1 gain = 350 uA

The loop filter of PLL1 is not changed from the standard that comes with the EVB (100 nF plus 680 nF and 39kOhms)

With these settings the PLL1 does not lock. Any ideas? With the standard configuration (CLKin 122.88 MHz and VCOout 122.88 MHz) all seems to work fine.

Best regards.

  • Two possibilities:

    1) The PLL1 Tab, R divider value is linked to CLKin1_R.  If you use CLKin0 or CLKin2, then you need to adjust the R value from the Bits/Pins page.  You can still update the PLL1 _ R value to reflect proper frequencies

    2) The VCXO has a pull range of +/- 20 ppm (min).  Due to this narrow window, it is possible if your clock source is +/- 50 ppm, maybe it won't lock.  Also, I notice that the 1.15924 MHz input / 2 * 212 = 122.87944 MHz VCXO frequency.  Is approximately -4.5 ppm off.


    A debugging tip is on the 'Other' page to set the PLL1_LD_MUX = PLL1 R / 2 and PLL2_LD_MUX = PLL1 N / 2, then probe these outputs with an oscope to see the the phases the phase detector sees.  If these waveforms have constant phase offset, then device is locked.  You can also measure the frequency to see that divide is working as expected (for example, see #1 above).  Also observing VCXO tuning voltage will provide some feedback as to why the device is not locked.  I.e. is the VXCO railed high or low, or does it have a constant voltage which should represent a locked operating condition.

    73,
    Timothy