Good morning, I am using a LMK04828 evaluation board (EVM) and I want to generate some clocks from a base clock at input CLK1 of 1.159245 MHz.
These are the settings:
CLK1 = 1.15924 MHz
PLL1 R counter = 2
PFD frequency = 579.6225 kHz
PLL1 N counter = 212
VCXO frequency = 122.88 MHz
CP1 gain = 350 uA
The loop filter of PLL1 is not changed from the standard that comes with the EVB (100 nF plus 680 nF and 39kOhms)
With these settings the PLL1 does not lock. Any ideas? With the standard configuration (CLKin 122.88 MHz and VCOout 122.88 MHz) all seems to work fine.
Best regards.