Experiencing interesting or weird things from this PLL.
1. We configure it to single PLL with internal VCO and OSCin is 100MHz.
register R11 bit[31:26] = 0x6
2. We are hoping to have 250MHz outputs on CLKout0/1/2/3/4/5/6/7 and CLKout8/9 as optional, in which 0 ~3 are LVPECL and 4 ~ 7 are LVDS
3. We can get proper outputs (250MHz) from CLKout6/7/8/9 but not CLKout0/1/2/3/4/5.
Were anythings missing? Thank you.
