LMK01000 Clock Input Power

Calvin Field

Q1: What is the approximate differential input impedance for the CLK0 and CLK1 inputs?

Q2: In the Electrical Characteristics table is the input clock power specification (Pclkin) range given differential input power or power per input pin as implied by the parameter description? Just need to verify.

Thanks,

Calvin

over 10 years ago

0 Timothy T over 10 years ago

TI__Mastermind 28590 points

I don't have SDD11 for this device. We have some impedance measurements on the single ended inputs. What frequency input are you using? I recommend a 3 dB pad for high frequencies for matching at high frequencies. At 800 MHz input impedance is approximately 31 ohms - j 192 ohms.

Power is given for single ended input.

73,
Timothy

0 Calvin Field over 10 years ago in reply to Timothy T

Prodigy 180 points

The input clock frequency is variable from 1 to 500 MHz. Ostensibly I just need to know whether the CLKIN ports are to be treated as high impedance or internally terminated to 50 Ohms. There is a lot of guidance given in the data sheet for terminating the outputs but I did not see anything on terminating the inputs.

0 Calvin Field over 10 years ago in reply to Calvin Field

Prodigy 180 points

That is actually a question, is the CLKIN port internally terminated to 50 Ohms?

0 Timothy T over 10 years ago in reply to Calvin Field

TI__Mastermind 28590 points

It is not internally terminated to 50 ohms. Theoretically it is high impedance, except that as frequency increases, the impedance is reduced to due capacitive effects.

I would suggest a 3 dB pad for input termination. I think this is the simplest option.

73,
Timothy

0 Calvin Field over 10 years ago in reply to Timothy T

Prodigy 180 points

Thank you. That answers my question.

Clock & timing

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LMK01000 Clock Input Power