LMX2592: PLL switching speed

Hi Shaun,

Thank you for your interest in our products. We received your question and will be answering it as soon as possible. We appreciate your patience.

Best Regards,

Julian

Hi Julian,

Any update?

Thanks.

Shaun,

We have been investigating this and it turns out that the 22 us lock time calibration graph was done by programming a register value (R4) that is not disclosed in the datasheet.   WHat we are doing is planning to update hte datasheet with these new settings, but we are doing the characterization to ensure that these settings are robust and don't introduce any issues.

Regards,

Dean

Hi Dean,

Any feedback on the original 2 questions?

The timing simulation result obtained is from the simulation SW TI Platinum Sim, not computed from TI datasheet.

Thanks.
 

Hi Dean,

Any feedback?

Thanks.

Hi Dean,

Any feedback on the original 2 questions.

In addition, in the simulation software, there is a peak time & it is much longer than the total lock time. May I know what this peak time means & do I need to factor in the computation of total lock time?

Lastly, any plan to amend/release a revised datasheet?

Thanks.

Shaun,

I recommend downloading the new PLLatinum sim as we have upgraded it, including the VCO digital calbiration model.

The model models VCO digital calbration and analog lock time only.   The write speed is not factored, but this can be reduced down to very small by having a high speed data bus.  We do not have a timing diagram for the write speed.  One thing you might want to consider also is how you express your fraction.  For instance, if you write the fraction 1/2 as 10000000/2000000, then this involves writing to more registers and takes more write time.  As for the cold power up time, there are many register writes needed and this time is going to be more significant.

Regards,

Dean

Shaun,
The peak time should always be less than total lock time, If so, it is a bug. I will tell you that for the LMX2592, I noticed that the lock time has a bug if you use the VCO doubler. I plan to fix this along with your bug, which might be related.

Peak time is the time from the original frequency to the frequency farthest from the orignal frequency. It does not factor into the calculation of total lock time, but rather describes the shape. It makes more sense to talk about this when VCO digital calibration is disabled.

For the newest PLLatinum Sim, I have made the lock time model based on the programming settings in the datasheet. As we do not have the settings in a released datasheet yet, I did not model this.

As for the datasheet, we know that we can get the 22 us by programming register R4, but we are still verifying that for sure that there is no potential issue of this ever causing a mislock. So there is a plan to revise the datasheet and we are working on it, but I can not commit to a date.

Hi Dean,

Thanks a lot.

By the way, what is the typical and worst case cold power up time?

Cheers.

Dear all,

I write on this post 'cause I am interested in LMX2592 locking time too.
In my design I adopt a 100MHz as reference producing channels around 8500MHz.
I'm investigating the switching speed using the LMX2592 as fractional-N PLL using the PLLatinum software (downloaded this morning). Results I got are not so promising:
VCO cal = 288.5us
Analog lock = 39.1us
Total lock time = 327.6us
These time values does not change changing the frequency step.

On the LMX2592 datasheet the reported Lock Time is about 22us + 13us, could you comment on this discrepancy please?

Thank you
Luca

Luca,

This basically cycles back to your question on April 7, so let me summarize.

1.Yes, the LMX2592 is capable of locking in 22 us VCO calibration time as the datasheet says.

2. However, this requires programming of register R4, which is not disclosed in the datasheet

3.  PLLatinum Sim has been updated, but the fast VCO calibration time does not account for the register R4 programming, which is much slower

However, it does have a box for fast calibration, but this does not reflect the programming of register R4, only what is currently disclosed in the datasheet.

When the datasheet is updated and goes to the web, then PLLatinum sim will be updated.

4.  The datasheet is not out to the web yet, but we are working on it.   I would hope the timeframe for this happening is weeks, but I can not commit to a firm date.

5.  The VCO calibration currently only starts with the lowest end of the highest frequency core, so the start frequency has no impact.

Regards,

Dean

Regards,

Dean

Hi Dean,

In addition to... What is the typical and worst case cold power up time?

From the latest simulation SW, there is the fast cal option. Is there any 'penalty' if it is chosen? e.g.. frequency stability, accuracy etc.?

Thanks.

Hi Dean,

In addition to... What is the typical and worst case cold power up time?

From the latest simulation SW, there is the fast calibration option. Is there any 'penalty' if it is chosen? e.g.. frequency stability, accuracy etc.?

Thanks.

1) This is pure lock time and does not include powering and LDOs powering up. Programming time should not be a big contirbutor, and is easy to estimate. For cold power up time, this we havce not characterized well.

2) We do not have this diagram, although we do have one that shows the VCO switching through the cores.

Also, I am upgrading the PLLatinum Sim for Lock time and releasing this week. One bug was with the doubler with the LMX2592. The only comand in software needed to initiate the calibration is to set the FCAL=1, which is a 24 bit register. As for the other registers, you might find our TICSPro software useful as it shows all the registers.

Regards,
Dean

Hi Dean,

Page 12 of data sheet Fig 18.

It shows the voltage (or power equivalent) required for the ref clock. For single ended input at Vbias 3.3V, this means it requires min 2.3V & max 4.3V

Translating into dBm equivalent, it meas it requires 17dBm min & max 22dBm max.

It seems very high power is required as compared to other PLL in the market.

Can you please counter check if I make any mistake? Or let me know the vendor requirements in terms of dBm? My clock is 600MHz.

Thanks.

The "Vbias" does not mean supply voltage, but rather if there is a bias voltage of the signal. Note that our part is AC coupled so all we care about is the swing, not the DC offset. This shows a differntial signal of 0.5Vpp per side or a single-ended of 1Vpp. Note that the power level to our chip is independent of the bias voltage as it is AC coupled.

Regards,
Dean

Hi Dean,

We are considering using the LMX2592 in our new radio design. We have a requirement for 50us hopping time, which means we need to calibrate the VCO and have the PLL settle under the 50us time. According to your datasheet and your posts this is possible but, we have not seen the simulator nor the evaluation board achieve this, which is a bit of a risk for us to use it. We have measured performance from an LTC part that achieves this lock time but, we would like to see if the TI part can beat it in terms of phase noise and spur levels.

Any update on the locking time with register 4 access and the programming tool's ability to access it? Can you provide the part settings you setup to achieve your datasheet's performance?

thanks,
Nathan