LMK04821 no longer locks on PLL1

The DLD reports unlock, Vtune reports lock.  When you check the output frequency using a frequency counter or SA, is the frequency on target and just DLD reporting unlock?

Given that your Vtune for VCXO is centered but PLL1 DLD is not asserted.  I would normally except some leakage issue associated with a lower VCXO input impedance and a low phase detector frequency.  However, I reviewed your programming in the other thread and it shows a phase detector of 24.576 MHz (high PDF reduces impact of leakage), and if you're using CVHD-950-122.88 MHz, that VCXO has high input impedance.

Could you program PLL1_LD_MUX or PLL2_LD_MUX = 0x13?  This puts the device into a not disclosed PLL1 analog lock detect output.  Is this output stable pulses?  What's the width of the pulse?  If the pulse width is too large relative to the PLL1_WND_SIZE setting, then device can be locked but DLD not reflect.  Can you provide a screenshot?

  - If not stable, a next test could be to output PLL1_N/2 and PLL1_R/2 to see which one is not providing expected output frequency.

73,
Timothy

Hi,
The VTUNE sits at midrail but the first PLL is clearly not locked. There's a small frequency error ( 100's of Hz depending on the day) and the frequency drifts around quite a bit (checked with an agilent N9020A spectrum analyzer). We have other boards with the same combination of VCXO and reference crystal and a different dual loop clock synth that locks well and the output in there is much much more stable.

Anyway, we just found something quite interesting. We did in fact manufacture 5 PCB's, first one and then the other 4. Turns out that the first one manufactured still locks perfectly and reliably, every single time. The thing is that we didn't have it available for about a month because the manufacturer didn't mount a press-fit connector well enought so it had to go back and then pass inspection but is still was badly assembled so back it went and and a month passed. The thing is, we're suspecting either an assembly error in some critical place in all other 4 cards related to the LMK that makes them barely able to lock (very likely hypothesis considering that we already identified two assembly errors in those second-batch cards, one of them would have killed them at power-on if not identified) or something related to a system management FPGA we have that has a previous firmware version in the first card than what's flashed in the other 4. That FPGA doesn't have SPI control nor access to DLD lines (those are connected to the main large FPGA in which the LMK configuration part hasn't changed) but it has access to CLKin sel lines (which we use as reference loss) and maybe it's doing something nasty in there.

Either way it looks like the problem doesn't lie in the LMK, tomorrow we'll dedicate the day to investigate and I'm pretty confident that we'll find the culprit and get all of them to lock.

Thanks for your answer.
David

David,

The fact that PLL1 Vtune is centered, suggests that PLL1 should be locked.  Two exceptions: CP leakage too great (as discussed in last email with test), or that you are in open loop mode.

Based on the programming you've provided (HOLDOVER_EN = 0; HOLDOVER_HITLESS_SWITCH = 0; FORCE_HOLDOVER = 0), you shouldn't be in open loop mode, but just in case...  The LMK04821 POR starts in holdover, if the LMK04821 enters holdover, it can remain in holdover until the output phase of PLL1 R and PLL1 N align.  In cases with a low phase detector frequency (yours is not low at 24.576 MHz), it can take a long time to exit holdover.  Of course, with your programming disabling holdover, the device would exit holdover, but to test the open loop:

As a sanity check, with MAN_DAC_EN = 1, TRACK_EN = 0, set MAN_DAC = 200, is voltage ~0.64 V = 200/1023 * 3.3 V

As a sanity check, with MAN_DAC_EN = 1, TRACK_EN = 0, set MAN_DAC = 200, is voltage ~2.58 V = 800/1023 * 3.3 V

I did create a Clock Architect sim for your design you can refer to below, I would suggest designing a loop bandwidth with a phase margin for PLL1 of closer to 50 degrees.  This will give your jitter cleaning a better 'cut' into any noise from reference:

http://webench.ti.com/wb5/OpenPublicSharedProject.jsp?id=32967A2F160684FB&s=c

73,
Timothy