LMK04828 continuous SYSREF settings

KI said:

1. I would like to set LMK04828 to output continuous SYSREF.

Follow table 1 from LMK0482x datasheet for continuous sysref, specific to continuous SYSREF:

• SYNC_MODE = X (don't care)
• SYSREF_MUX = 3
• SYSREF_PD = 0
• SYSREF_DDLY_PD = 0
• SYSREF_PLSR_PD = 1 (or don't care)

As per the sequence in Setup of SYSREF example you need to set SYNC_DIS#/SYNC_DISSYSREF = 1.

0x139: 0x03 [SYSREF_CLKin0_MUX = 0]
0x13e: Don't care
0x13f: As required for your architecture usage of device, nothing relating specifically to continuous SYSREF.
0x140: As required for your architecture usage of device, however, bit 2 = 0 [SYSREF_PD], bit 1 = 0 [SYSREF_DDLY_PD], not necessarily required, but you may set bit 3, SYSREF_GBL_PD = 0.  This only take effect if the
0x143: bit 7 = 0 [SYSREF_DDLY_CLR], bit 4 = 1 (SYNC_EN).
0x144: 0xff;  Note however, starting SYSREF is a multi-step process if you want all outputs to be synchronized together.  You need to have 0x144 = 0x00 first, do a sync, then operate SYSREF as desired.  Please refer to 9.3.2 of datasheet.

I've also attached a document which may help you.  Key Points to setting up SYSREF on LMK0482x.pdf

KI said:

2. how do i use the SYNC pin? is this the same as the ADC12J4000 SYNC~ signal?

The SYNC can be used in multiple ways.  Table 1 from datasheet should help explain them.  Bottom line is that SYNC and SYSREF functionality share the same distribution bus.

You can use SYNC to request continuous sysref by programming SYSREF_REQ_EN = 1, SYSREF_MUX = 2, SYNC_MODE = 0, SYSREF_PLSR_PD = 0.  You cannot invert polarity of this pin function.

Note that CLKin0 can also be used for some SYNC functions, and where possible I recommend this because CLKin0 is a high speed clock input vs. slow CMOS input.  Also, noise or toggling SYNC pin can result in noise on VCO, particularly VCO0.

The SYNC pin is a convenience if a hardware interface is of value.  Because you can fake a pin toggle by toggling the SYNC_POL_INV bit.

KI said:

3. if i want to adjust the SYSREF digitally delay, what is the programming sequence for the registers?

To adjust the SYSREF_DDLY, which is a global SYSREF digital delay and device clock output delay, ensure SYSREF_DDLY_PD = 0 and all CLKoutX_DDLY_PD = 0.  Then execute a SYNC (best done with a signal, as per Pin or SPI SYNC on Table 1).  You also need to ensure that SYNC disable bits are clear.

Alternatively, you may simply adjust the half step delay registers or the local SYSREF digital delay, SDCLKoutY_DDLY which does not require a re-sync.

73,
Timothy

Hello,

The output of a specific DCLKoutX and SDCLKout(X+1, that is, its corresponding Y) should be the same when SDCLKout(X+1)_MUX = 0 (Device Clock).

Possible difference is:
SDCLKoutX_POL/SDCLKoutY_POL are not the same value, this would result in an inversion of the output clocks.

Another possible difference is the DCLKoutX_FMT and SDCLKoutY_FMT could be set to different formats, like LVDS and LVPECL20. Ensure these are the same.
- Further, if the output termination is not the same, then again, it is possible the output waveform isn't the same.

To comment further, I'd have to see a screen shot of what you're seeing.

73,
Timothy