CDC208

Robert Grube

Other Parts Discussed in Thread: CDC208, LM311

How to terminate unused single-ended clock output pins on the CDC208; design of output load for used clock outputs

How do I terminate unused single-ended clock output pins on the CDC208?

I've researched this quite extensively; and the data-sheet itself doesn't provide an answer (I'm using the CDC208 for a PCB, to

drive clock outputs to an SMA connector. Clocks are 2.5V, 4.75MHz, RZ logic; and 3.3V, 13.9KHz, RZ logic). Some good options, I believe, would be:

1. To use a 50-ohm SM resistor to the ground plane on the PCB, or to a 'poured' ground region that connects to the ground-plane through a via;

2. To use a 50-ohm SM resistor in series with a SM RC-network to ground (a 1k-resistor in series with a 0.01uF capacitor connected to ground);

3. To let the pin float;

4. To assume that some internal impedance exists within the IC, and to use a 33-ohm SM resistor to ground, with the same following SM RC-network in

option #2 above;

5. To use option #2, but with a following LM311 unity-gain buffer with resistively-tied (100k-ohm) inputs, and with the output floating.

Second question: Does Figure 1. in the CDC208 data-sheet illustrate the proper load-network for all of the used clock outputs? I.e., 50pF capacitor to ground, followed by a 500-ohm resistor to ground, followed by a 500-ohm resistor in series with the output? With no 50-ohm resistor in series with the Output BEFORE the 50pF capacitor?

over 9 years ago

0 Timothy T over 9 years ago

TI__Mastermind 28550 points

Hello,

See my input below:

Robert Grube said:
How to terminate unused single-ended clock output pins on the CDC208; design of output load for used clock outputs

I recommend your option #3. Typically CMOS outputs are designed to drive high impedance, capacitive loads. If you leave the output floating you will have a high impedance, low capacitance load, I'd say floating is the ideal CMOS load.

Since the typical CMOS load is high impedance, all the signal gets reflected and source termination is used prevent reflections as you suggest in #4, but this impedance matching won't be required as your trace length will be so short, there will be no reflections to worry about.

Robert Grube said:
Second question: Does Figure 1. in the CDC208 data-sheet illustrate the proper load-network for all of the used clock outputs? I.e., 50pF capacitor to ground, followed by a 500-ohm resistor to ground, followed by a 500-ohm resistor in series with the output? With no 50-ohm resistor in series with the Output BEFORE the 50pF capacitor?

I think this test circuit matches the near extremes some of the use cases (again, considering that typically it will drive a high impedance, capacitive load). In the 2x Vcc the CMOS output needs to drive a load that is pulled high through 250 ohm to Vcc. In the ground case, the CMOS output needs to drive an load which is 250 ohms to ground. Considering the 5 V Vcc, both of these conditions (+/- 20 mA) are slightly with-in the max recommended operating condition for Ioh (-24 mA) and Iol (24 mA).

The open case would represent driving a "higher" impedance CMOS load with 500 ohms impedance to ground (aggressive, as I think typically input impedance to a CMOS circuit is much higher).

Hopefully this helps.

73,
Timothy

0 Robert Grube over 9 years ago in reply to Timothy T

Prodigy 70 points

Thank you, Timothy!

I have one more question regarding the CDC208, if you don't mind:

It has been suggested that the proper termination on the output clock pins of the CDC208 for my usage (the clock outputs of
the CDC208 on my board will be driving SMA connectors soldered directly to the PCB), is a 22-ohm series resistor. That is,
the 22-ohm resistor will be in series with the stripline on which the clock signal will travel. Similarly, where one of the output
clocks will be driving the clock-input of TI's Single Positive-Edge D-Type Flip-Flop, there should also be a 22-ohm series
resistor.

The assumption in both of these cases, I believe, is that there is some internal impedance on the output lines of the CDC208;
which, when added to that of the 22-ohm resistor, combines to create a 50-ohm impedance which should load the clock
outputs nicely, and eliminate most reflections.

Is this assumption correct? How do you suggest that the clock output pins of the CDC208 be best terminated?

Thanks in advance for your time,

Robert

0 Robert Grube over 9 years ago in reply to Robert Grube

Prodigy 70 points

Sorry, one more -- clock inputs to the CDC208 from the SMA, I believe, should have 50-ohm series termination resistors. Is this correct, or should one assume impedance on the inputs inside the chip, and size these resistors differently?

Thank you!

Robert

0 Timothy T over 9 years ago in reply to Robert Grube

TI__Mastermind 28550 points

You're right about the the source termination, trying to get to 50 ohms by combining output driver impedance with some series resistance. As for this device, I'm not sure the output impedance. However the measurement test circuit doesn't show usage of such source resistor. I would consider placing a footprint for the source resistance, if not required a 0 ohm can be placed.
> I'll notify someone else to see if they know more about the CDC208 output and recommended termination.
> Based on the measurement circuit however, there was no external "Rs" placed.

--

As for handling the input. You could either source terminate with series "Rs" to have output have a 50 ohm source (22 to 33 ohms?), or load terminate with 50 ohms to ground close to CDC208 input.

The CDC208 has a high impedance input. If you do place a 50 ohms to ground, then you need to be sure the driver can drive the Voh level. What is necessary is to DC couple. You can improve about this by placing a cap in series with the 50 ohms to ground, this eliminates the difficulty of DC driving the 50 ohms straight to ground but does add more capacitive load.

I typically suggest driving it a high impedance load it is and using the source resistance termination scheme. However any combination is ok provided it meets you're requirements.

73,
Timothy

0 Robert Grube over 9 years ago in reply to Timothy T

Prodigy 70 points

Hi Timothy;

Thank you very much for your answer.

I'll wait for any further recommendations from your CDC208 contact regarding the recommended termination.

Also, one last (last!) question: Since we are using a 4.75MHz clock through the CDC208, would you recommend X2Y decoupling capacitors (1.0uF and 0.1uF) on the VCC supply pin from Johanson Dielectrics, given the fact that the
clock is operating in the low-MHz range? These capacitors have low parasitic inductance and lower loss of
capacitance at higher (MHz) frequencies.

Or is this a non-issue, given the fact that our power supply has a loop-bandwidth of only a few kilohertz?

Mouser sells Johanson's X2Y Multi-Layer Ceramic Capacitors (MLCCs) in the 0603-size with their X7R and X5R
dielectrics:

www.mouser.com/.../

www.mouser.com/.../

Thanks again,

Robert

0 Robert Grube over 9 years ago in reply to Timothy T

Prodigy 70 points

Hi Timothy;

Earlier, you wrote, in regards to the CDC208:

> I'll notify someone else to see if they know more about the CDC208 output and recommended termination.

I was wondering if you found anyone who had an accurate knowledge of the internal output impedance yet.

Also: I did some capacitance calculations regarding the load I am expecting the CDC208 to drive. My load is approximately ~112pF, max. And, the clock frequencies I will be using are below 5MHz (with a wavelength longer than the entire clock path length). Is it a safe assumption to assume the CDC208 can handle this load, without distortion of Trise and Tfall from the CDC208's clock outputs, and that therefore no buffering is needed?

Thank you for your time,

Robert Grube

0 Patrick Kammermayer over 9 years ago in reply to Robert Grube

TI__Expert 5325 points

Hello Robert,
I need to check internally about the output drive. But from VOL/IOL you get something in the range of 20 Ohm.
The test load from the data sheet is usually designed as a lumped load, meaning that the PCB we measure on is far below the wavelength.
The rise and fall times are characterized using the 50pF load. The frequency applied in this characterization was 10MHz max, according to footnotes A,B of Figure 1.

Best regards,
Patrick

0 Robert Grube over 9 years ago in reply to Patrick Kammermayer

Prodigy 70 points

Hi Patrick;

Thank you very much for your answer and your time!

I will use this value for the internal impedance and see what I get.

Thanks again,

Robert

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