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LMK04828 ClkIn1 max/min frequency

Jon Reyland
Intellectual 280 points
Other Parts Discussed in Thread: LMK04828, DAC37J84

Hello,

My LMK04828 is on a DAC37J84 EVM card.  I am trying to use Nested 0-delay Dual Loop Mode.

This works (PLL1 and PLL2 locked): 

ClkIn1 = 12.288 MHz, VCO1 =2949.12 Mhz, SysRef divider = 240, DAC Clk = 983.04 MHz, FPGA Clk = 245.76 MHz,

This does not work (PLL1 not locked,  PLL2 locked):

ClkIn1 = 12.288 MHz, VCO0 = 2457.6 MHz, SysRef divider = 200, DAC Clk = 491.52 MHz, FPGA Clk = 122.88 MHz

I have no idea what is the cause of this problem.  Are there limits to any of these quantities?  Are they published?

Thanks,

John Reyland

Rockwell Collins, Inc

  • 0
    TI__Mastermind 28560 points
    Hello John,

    I don't have enough info to tell you what's going on. Full programming maps for each case would be needed along with VCXO frequency. Perhaps the following can help...

    Are you using the SYSREF Divider as the feedback frequency to PLL1 N? If so, it appears you've properly adjusted SYSREF Divider to provide a 12.288 MHz clock to N divider, so your PLL1 N divider wouldn't need to change.
    > If you are pulling from DCLKout6 or DCLKout8 and they is providing say, your FPGA clock, then you would need to adjust the PLL1 N value to compensate for the different feedback frequency.

    Another technique you might use to figure out what's going on between the two configs is to set one of the status outputs = PLL1 N/2 output. For example set PLL2_LD_TYPE = 0x03 (Output, push-pull) and PLL2_LD_MUX = 0x0c (PLL1_N/2). This will let you know what your feedback frequency is compared to what you're expecting. Note you can also set the other Status pin to (PLL1_R/2) and see the reference signal to confirm that frequency is also as you expect.

    73,
    Timothy
  • 0 in reply to Timothy T
    Intellectual 280 points
    Hi Timothy,
    I really appreciate your prompt reply as I am on a tight schedule to get this working. Here is a complete picture of my setup. As noted, this worked with 983.04 MHz sample rate. However nested 0 delay dual loop mode with 491.52 sample rate is turning out to be difficult.

    Please let me know ASAP if you see any problem or if the LMK04828 has an undocumented quirk. Since you have access to TI DAC37J84 EVM, maybe you could try this there.

    Thanks Very much
    John Reyland
  • 0 in reply to Jon Reyland
    Intellectual 280 points

    Hi Timothy,

    I really appreciate your prompt reply as I am on a tight schedule to get this working.  Here is a complete picture of my setup.  As noted, this worked with 983.04 MHz sample rate.  However nested 0 delay dual loop mode with 491.52 sample rate is turning out to be difficult. 

     

    Please let me know ASAP if you see any problem or if the LMK04828 has an undocumented quirk.  Since you have access to TI DAC37J84 EVM, maybe you could try this there.

     

    Thanks Very much

    John Reyland

    Screen snips showing LMK04828 setup on TI DAC37J84 EVM (new board, default jumper settings)

    DAC37J84 EVM drives LMK04828 OSCIN pin with a 122.88MHz VCXO

    John Reyland, Rockwell Collins, Inc.

    Problem: With these settiings, PLL1 is not locked (D6 off) and PLL2 is locked (D7 on)

    Intent is to setup Nested 0-delay Dual Loop Mode. A 12.88 MHz, 13 dBm external osc is connected to J17 (LMK04828 ClkIn1). 

    Both PLL lock up with the following changes from what’s below:
    VCO1 =2949.12 Mhz, SysRef divider = 240, DAC Clk = 983.04 MHz, FPGA Clk = 245.76 MHz,

     

  • 0 in reply to Jon Reyland
    TI__Mastermind 28560 points
    Hello,
    Can you try putting at higher frequency input to CLKin1, for example, 122.88 MHz? 12.288 MHz even at 13 dBm has a slew rate of about 0.1 V/ns. We spec a minimum of 0.15 V/ns. I wonder if there is some marginal performance based and based on the different configuration, the device locks or does not lock.
    - Another experiment I can't recommend for normal operation with a +13 dBm signal is to set CLKin1 to Bipolar mode (max 2.4 Vpp single ended), you may gain a bit more sensitivity (or not) with your setup.
    - I think this could be your issue.
    - If you continue to have issues, please check frequency of Status LD1/LD2 Mux to output PLL1 R/2 and PLL1 N/2 to see what's going on at the PLL1 phase detector.

    Other comments on the configuration:
    - FYI, Setting Track EN = 1 and Man DAC EN = 1 means holdover will not use the tracked value, unless you are manually reading back the tracked value and programming the MAN_DAC value with the readback value.

    I'm in the clocking group and don't actually have the specific eval board you are using to duplicate the test with.

    Note that we don't recommend continuous SYSREF during sampling operation due to crosstalk. It is good for system design/debug, and also for extended SYSREF pulse generation.

    73,
    Timothy
  • 0 in reply to Timothy T
    Intellectual 280 points
    Hi Tim,

    Thanks for the interesting comments. I do not see how CklIn1 could have much to do with this problem because I had PLL1 and PLL2 locked with the following:

    ClkIn1 = 12.288 MHz, VCO1 =2949.12 Mhz, SysRef divider = 240, DAC Clk = 983.04 MHz, FPGA Clk = 245.76 MHz,

    Without ANY change to ClkIN1 frequency or power level, this does not work (PLL1 not locked, PLL2 locked):

    ClkIn1 = 12.288 MHz, VCO0 = 2457.6 MHz, SysRef divider = 200, DAC Clk = 491.52 MHz, FPGA Clk = 122.88 MHz

    Also, Kang Hsia in the DAC group has helped me experiment with this setup in the past. I think he said there was a frequency that ClkIn1 would not accept maybe it was 49 MHz. Would you double check with him please?

    I appreciate that LMK04828 has a rise time spec, however I think there is something else going on here.

    Thanks,

    John Reyland
    Rockwell Collins, Inc
  • 0 in reply to Jon Reyland
    TI__Mastermind 28560 points
    Ok, please let me know the result of the test where you measure PLL1 N/2 and PLL1 R/2.

    73,
    Timothy