Xilinx Ultrascale design collateral/ app notes for driving CDCLVD2102 or similiar?

Michael Raleigh

Other Parts Discussed in Thread: CDCLVD2102

Hello,

I have a customer that needs to drive an LVDS clock into a 1.2v bank (ddr4) in a xilinx ultrascale design. Do we have any collateral they could use to help in this? They're using a 2.5V CDCLVD2102 and the common mode is too high to run directly into the FPGA, the assumption currently is that they need to AC couple it?

Thanks,

-Michael

over 9 years ago

0 Alan O over 9 years ago

TI__Mastermind 32575 points

Does the FPGA's input buffer have internal input termination and biasing? If so, then AC coupling is the easiest way to interface. They should also confirm that the driver's Vod specs meet the receiver's Vid specs.

Alan

Clock & timing

Clock & timing forum

Xilinx Ultrascale design collateral/ app notes for driving CDCLVD2102 or similiar?