LMX2492 OSCin (No reference out)

Steve Usary

Other Parts Discussed in Thread: LMX2492

I am presently working on a design using the LMX2492. I am unable to get an output from the phase detector. I’m using the TRIG2_MUX pin as a test point for trouble shooting. I set register 0x25 to a value of 0x82 which should set the TRIG2_MUX (pin 21) to Output R Divide/4 and the output driver to Pullup/Pulldown Output according to Tables 6 and 7 of the datasheet. I’m driving the OSCin (pin 9) with a 250 MHz sine wave at 1 VPP capacitively coupled. The GND/OSCin* (pin 10) is grounded. The PLL_R divider is set to 3 (Reg 0x19) and the PLL_R_DIFF and OSC_2X bits in reg 0x1B are set to zero. I would expect to get a 20.8333 MHz output on the TRIG2_MUX pin but I only get a constant low output.

The control of the chip by SPI seems to be working fine. I can write and read back any register.

What am I doing wrong here?

Should the GND/OSCin* pin be tied to ground as shown in the schematic in section 9.2 and as stated in section 8.3.1 of the datasheet?

I’ve tried various frequencies and levels at the OSCin pin and various settings of the PLL_R divider but I can get no transitions at all on the TRIG2_MUX pin. If I set the TRIG2_MUX pin to Output Read back I can see the register data coming out so I know the pin can change state.

over 9 years ago

0 Julian Di Matteo over 9 years ago

TI__Expert 4085 points

Hi Steve,

Thank you for your interest in our products. We received your question and will be answering it as soon as possible. We appreciate your patience.

Best Regards,
Julian

0 Noel Fung over 9 years ago in reply to Julian Di Matteo

TI__Guru** 110880 points

Hi Steve,

TRIG2_MUX is at register 0x25h. The value of Output divider R/4 should be 0x11h.

0 Steve Usary over 9 years ago in reply to Noel Fung

Prodigy 50 points

Hi Noel

According to the LMX2492 datasheet Tables 6 and 7, if I set register 0x25h to 0x11h this would select Open Drain output and Input TRIG2 for the TRIG2_MUX pin. Am I reading the datasheet wrong or do you have other info? See post below.

Thanks
Steve

0 Steve Usary over 9 years ago in reply to Steve Usary

Prodigy 50 points

Noel,

I think I see where you're coming from. The MUX selection value (Table 7) would be 17 dec. This would be 0x11h. However it occupies the upper five bits of the data Byte so shifting it up 3 bits would give 0x88h. The lower three bits of reg 0x25h are for the terminal state of the TRIG2_MUX pin (Table 6). Setting the terminal state to Pullup/Pulldown Output would be an 0x02h. Anding the two together would give a value for reg 0x25h of 0x8Ah. I miscalculated 0x82h. This would set the TRIG2_MUX pin to Output R Divide/2 not Output R Divide/4.

If I set Reg 0x25h to either 0x82h or 0x8Ah I should still get the divided down reference on the TRIG2_MUX pin and I don't.

Thanks
Steve

0 Steve Usary over 9 years ago in reply to Steve Usary

Prodigy 50 points

I'm presently talking with Dean Banerjee (TI) about the problem. He's investigating if there needs to be a way to select single ended OSCin that's not noted in the datasheet.

0 David Langan over 8 years ago in reply to Steve Usary

Intellectual 270 points

I'm having the same problem right now in trying to get the Output R Divide/4 working on the MUX line. Did you or Dean Banerjee come up with a solution?

Regards,

David

0 Noel Fung over 8 years ago in reply to David Langan

TI__Guru** 110880 points

I don't have problems configure it to output R/4 at either MUXout or TRIG2 pin.
For example, I set TRIG2 pin to output R/4 with push-pull signal level.
R35[4] = 0b
R37[7:3] = 10001b; R37[2:0] = 010b. In other words, R37 = 0x258Ah

0 David Langan over 8 years ago in reply to Noel Fung

Intellectual 270 points

Noel,

I was able to enable N Divide/4 on MOD_MUX by writing 0x9A to the register. No dice with R Divide/4. I think the issue is that the OSC drive signal is too weak. It's just above 0.25 V pp as specified on the data sheet. Would that be a possibility?

Will try a stronger drive signal next week.

David

0 Noel Fung over 8 years ago in reply to David Langan

TI__Guru** 110880 points

Hi David,

R/4 is taken out from the R-divider, the signal strength of OSCin is therefore not important. As long as your PLL is locked, you should get the right signal out.

0 David Langan over 8 years ago in reply to Noel Fung

Intellectual 270 points

PLL is not locking which is why I am trying to verify the R and N divider outputs. I am able to drive the charge pump output to the +5V/0V rails by switching the CPPOL bit and watch the VCO output move to its upper and lower frequency limits.. I can drive the VCO to an intermediate frequencies as well by pulling the charge pump output to an intermediate voltage when probing it with a multimeter.

0 Noel Fung over 8 years ago in reply to David Langan

TI__Guru** 110880 points

I see. Please try again with a higher OSCin signal swing.

0 David Langan over 8 years ago in reply to Noel Fung

Intellectual 270 points

I was able to get the LMX2492 to lock with a 0.3-Vpp drive signal. I also confirmed an output on from R Divide/4 on the MOD line.

There is a large phase noise pedestal only about 15 dB down though so perhaps the drive level is still not sufficient. I can reduce the noise if drop the charge pump current to 100uA but the output still has some modulation spreading the energy across a 500 kHz span. Thanks again Noel.

0 David Langan over 8 years ago in reply to David Langan

Intellectual 270 points

Increasing the reference input voltage to ~1.0-Vpp eliminated the noise pedestal. The issue was R Divider sensitivity as described on page 64 of PLL Performance Design and Simulation 5th Ed.

David

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LMX2492 OSCin (No reference out)