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LMK00804B duty circle

Minglei Zhang
Prodigy 90 points
Other Parts Discussed in Thread: LMK00804B

Dear all,

Can LMK00804B support 50MHz 20% duty cycle input clock? If yes, how about the additive jitter and the duty cycle of single-ended LVCMOS output clock?


Input of LMK00804B: 50 MHz 20% duty cycle LVDS clock to CLK/nCLK pins with Slew Rate more than 3V/ns.
Power Supply of LMK00804B: Core supply is 3.3V; Output supply is 1.5V.

Thanks in advance.

Regards,

Minglei

  • 0
    TI__Mastermind 24205 points

    Hi Minglei,

    Yes. The LMK00804B can support a 20% duty cycle input reference

    The datasheet spec for the duty cycle is 45%-55% for a 50% input duty cycle reference. With a 20% duty cycle on the input, the expected variation in the output clock duty cycle is 15%-25%. However this would hold true if VDD=VDDO=3.3V. Since the supplies are not the same, there could be additional degradation (condition not speced in the datasheet)

    The additive jitter should not really suffer because of the duty cycle distortion on the reference input.

    Regards

    Arvind Sridhar

  • 0 in reply to Arvind Sridhar
    Prodigy 90 points

    Thanks Arvind, The answer is really helpful.