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CDCM6208V2 frequency accuracy problem

Simon Guignard
Prodigy 180 points

Hello,

I am currently working on a CDCM6208V2 Evaluation Board.

I use the GUI to configure my chip.

My configuration is the following:

SECp = crystal input 10 MHz

M = 125

N = 6250

f_PFD = 80 kHz

Loop Filter = configuration 4 (p.16 Evaluation Board datasheet)

f_VCO = 3000 MHz

PSA = 6

PSB = 6

PRE = 2

FRA = 122.0703125

Y4 = LVCMOS 2.048 MHz, 0 PPM

As you can see I should obtain 2.048 MHz on Y4 but I measure 1.93113 MHz (about 5.71% error).

I also tried to use Y0 with an integer divider of 50 (Y0 LVPECL output 10 MHz) to test the accuracy but I measure 9.4337 MHz (also about 5.71% error).

I would like to know where this error comes from. (VCO frequency?).

Also I am forced to put 2.171943 MHz for Y5 on the GUI (PRE = 2, FRA = 115.1043176) to measure 2.048 MHz in output.

This method to get the frequency I want in output bothers me a little bit.

Thank you for your help,

Simon

  • 0
    TI__Expert 4400 points

    Hi Simon,

    I think the PLL is not locked and the VCO is operating in open loop. That is why you see the error. Please read back register 21, bit 1. If it is "0", then reference clock is detected and means that loop filter design could be the issue. If it reads back "1", then reference clock is not detected and we need to look at the input interface.

    also is there any reason you choose to run at 80kHz update rate on PLL? You can keep the update rate at 10MHz and just use N divider of 50 with PS = 6. This way, you can use on-board loop filter settings to atleast get the PLL to lock. Then I can work with you to select right loop filter component values for best performance.

  • 0 in reply to Madhu Balasubramanian
    Prodigy 180 points

    Hi Madhu,

    I've red the R21.B1 and it is "0" as expected (reference input present).

    The problem has been solved when I literally changed nothing at all and the PLL ended up being locked for some reason with the configuration I described earlier. This happened yesterday. Today it got back to the frequency error.

    I've been using 2 different loop filter, M and N configurations during my tests :

    C1 = 5u ; C2 = 100u ; C3 = 562.5p ; R2 = 100 ; R3 = 4010 ; M = 125 ; N = 6250 (f_PFD = 0.08 MHz)

    and

    C1 = 1p ; C2 = 15n ; C3 = 242.5p ; R2 = 330 ; R3 = 100 ; M = 1 ; N = 50 (f_PFD = 10 MHz) but in reality I do not use these values for C1, C2, R2, I use the on-board loop filters. By the way changing the loop-filter configuration doesn't seem to have any effect on the output signal, what should I see?

    Also I don't know if it has anything to do with my problem but since I've been using the board it has always been confused between the chip and the GUI. The "PLL Lock" and the "VCO Version" do not always match between on-board LEDs, GUI LEDs and register values.

    Thank you for your help,

    Simon