LMK04806 output blocked at 368Mhz (LVDS)

So as I understand, LVDS doesn't start / has a strange waveform at start-up.  But it continues and does not go away.

Are there other input termination options the FPGA offers?  Normally in AC coupled scenario FPGA should provide some R to Vcc/Gnd for biasing.  Is the FPGA possibly configured as high impedance input with no biasing?  What is Vcm of input on FPGA side of caps?

What is the size of the AC coupling caps for LVDS to the FPGA?  Is it possible to eliminate these for DC coupled LVDS?

73,
Timothy

Hi Timothy,
Thank you for your answer I appreciate a lot your help, after an hard week work I'm still in trouble with this device, I tried a way out, checking all the possible mistake or software cofiguration error but without success, also a reconfiguration is not possible.
I have also tryed to patch the board to transform the output in LVPECL, but my oscilloscope mislead me, I will retry on monday, but I'm not confident to see something different.

About your questions:
1)The FPGA's clock inputs for GTH SERDES of the can accept LVPECL or LVDS signals.
2) Seems impossible to change or tristate the input bias, see the following pictures, I will ask to our FPGA field application.
3) The VCM is 4/5 MGTAVCC (1V *4/5) = 0,8V
4) The partlist foresee 0,1uF the FPGA datasheet 0,01uF, I have changed the capacitor to the correct value with no success.
5) The FPGA datasheet do not foresee the DC scheme.

In attach, you can find the captured trace of the problem, I was able to catch also single-end traces of the positive and negative pins with a better probe/oscilloscope. (on monday I will retake the traces with a better format).

Thank you

Maxx

Before download

After bitstream download

Negative/positive pins

Hi Timothy,
Using the LVPECL scheme the problem disappear, good... but I need to understand why the LVDS AC coupling does not work, I will use the same FPGA with a LMK04828 on another board.
Thanks
Maxx

Hi Timothy, due to a lack of time, we will not perform the test suggested over the LVDS lines, I will in future use the LVPECL configuration when possible, seems to me that gives more reliability over the LVDS is that right ?

I take advantage of this chat to ask other questions on LMK family, if you feel the need to open another thread, just let me know.

I have to built a system that can handle a beamforming and MIMO RF front-end between two boards in a shelf, we will use a  mix of JESD DAC and parallel ADC triggered and governed via a FPGA present over each board.

Every board will mount a LMK04828 as main PLL, that in turn generates all the clocks for four parallel ADC, two JESD DAC and two RF front-end, in particulary we will generate 307.2Mhz for DAC and ADC and 122.88Mhz for the RF.

A reference clock signal coming from the main backplane will reach one of the two adiacent boards where will be fanout toward its LMK and over another backplane to the mate LMK.

Both the LMK over the to boards will recive a deterministic signal clock, the fanout buffer have a skew of less of 15pS, but one of the two boards will receive the reference signal with a delay of about 2nS (measurable) due to the lenght of the backplane.

The boards will receive the reference on CLKIN0 and CLKIN1 inputs at 19.22Mhz

Both the LMK will be configured to perform a  0-delay to the internal SYSREF divider mode to create a system wide SYSREF and phased clocks, obviously we have to compensate the outputs using PLL R/N delay SYSREF_DDLY and the output analog/digital  delay adjust.

The SYNC inputs for both the LMK will be triggered by board FPGA interconnected through a backplane.

We hope that this configuration can garantee a perfect synchronization to achieve +/- 25pS of shew between the radio reference clocks on the two boards and  give us a way to trigger the SYSREF with less stringent setup time for the SYNC input (backplane delay 2nS and FPGA delay). 

I have to understand if I'm on the right way and if from your experiance we can achieve our targets.

Thanks

Maxx

Hi Timothy, I really need your help, in particular I'm not sure that SYSREF will be aligned on the same phase on two boards also if the SYSREF dividers starts not at the same time, I'm have to stop my headache.
Maxx

Hi, thank you for your answer.
I can't wait your app note, I need to define as soon as possible this topic.

1) I may understand that the CLKin0 is better than the sync input, and i can arrange the hardware to use it, but it means that also the path and driver of my sync trigger is critic in the same way, contrary to what I had thought, is that true ?

2) Using the first method the 0-dealy will be done using the nested 0-delay dual loop mode with one of the DCLKout6/8 ?

3) If the SYSREF comes through the SYSREF_CLKin0_MUX will reset the output divider to rephase the clock and SYSREF output but will impose us to have a low skew between the clock 0 inputs of LMKs of the two boards, that in this moment is not possible in my design. Is that correct? (I have an fpga that generate the sync signal on each board), If I use the SYSREF_DIV also in the first method to reclock the SYNC/CLKin0 we do not have the synchonization between the boards because of unknown phase of the SYSREF_DIV. is that correct ?

4) The DCLKout6/8 in first method may be one of the generated clock frequency(eg 307.2M) or must be equal to a reference clock (may be impossible in my configuration)?

5) You say that In both the methods a reference clock frequency (input to the clk1) must be equal to the SYSREF, does it means that the PLL1 phase detector must work at the SYSREF frequency, imposing the CLKin1 R Divider equal to 1 ?

6) In the second method seems to me that we can relax the skew between the sync signal of the to two boards allowing us to transit into the onboard FPGA prior to trigger the LMK. Is that correct ?

7) You say that in the second method we have only one possible SYSREF frequency, that is what we have on our board. We have only one SYSREF but it can be configured to have different DAC sampling frequency.

8) The SYSREF frequency as far I know we need a 19,2Mhz or 9,6Mhz in one coniguration and a 7,68Mhz on 3,84Mhz in a second configuration of the board, but we will try to use a single pulse method to synchronize the board.
I suspect that we need a 7.68Mhz for handle the two configuration.

10) I this moment we have designed the board that can handle basically 4 references clock 10Mhz,16Mhz,19.2Mhz e 30.72MHz configuring the LMK in a dual loop configuration and an external VCO of 122.8Mhz (has the demo board).

I hope you can helpme ...
Thanks
Maxx

Hi Timothy,

Have a look at the attached schematic, I want use the LMK03200 as clock generator for the LMK04828 reference.

MaxxCLOCK.docx

Sorry, I've not had time to fully look into your design, but hopefully these immediate answers can accurate and of some use:

maxx said:

1) I may understand that the CLKin0 is better than the sync input, and i can arrange the hardware to use it, but it means that also the path and driver of my sync trigger is critic in the same way, contrary to what I had thought, is that true ?

I'm not sure I understand this, but yes, CLKin0 would need to have some specific timing arrangement to OSCin signal.  You are using dual loop with the input clock at 19.2 MHz and 122.88 MHz VCXO.

maxx said:

2) Using the first method the 0-dealy will be done using the nested 0-delay dual loop mode with one of the DCLKout6/8 ?

Nested 0-delay using SYSREF Divider.

maxx said:

3) If the SYSREF comes through the SYSREF_CLKin0_MUX will reset the output divider to rephase the clock and SYSREF output but will impose us to have a low skew between the clock 0 inputs of LMKs of the two boards, that in this moment is not possible in my design. Is that correct? (I have an fpga that generate the sync signal on each board), If I use the SYSREF_DIV also in the first method to reclock the SYNC/CLKin0 we do not have the synchonization between the boards because of unknown phase of the SYSREF_DIV. is that correct ?

There must be some low frequency signal between both boards to result in deterministic timing relative to that low frequency.  As I understand now with your 19.2 MHz, you can have deterministic timing for 19.2 MHz.  So if that is your SYSREF, great.  If your sysref is less than 19.2 MHz or not well related to 19.2 MHz, then you will need to have some external SYNC that connects to both boards.

maxx said:

4) The DCLKout6/8 in first method may be one of the generated clock frequency(eg 307.2M) or must be equal to a reference clock (may be impossible in my configuration)?

That needs to be SYSREF DIV and the SYSREF frequency as per above.

maxx said:

5) You say that In both the methods a reference clock frequency (input to the clk1) must be equal to the SYSREF, does it means that the PLL1 phase detector must work at the SYSREF frequency, imposing the CLKin1 R Divider equal to 1 ?

It's not strictly required for R = 1, but in reduced fraction of N / R, R must be reducible to 1.   So it is possible for PLL1 phase detector to be less than the reference (SYSREF) frequency.

maxx said:

6) In the second method seems to me that we can relax the skew between the sync signal of the to two boards allowing us to transit into the onboard FPGA prior to trigger the LMK. Is that correct ?

Not sure I fully understand this statement, to achieve determinism of SYSREF (what is your SYSREF frequency),.  Skew between the boards is not so much the issue provided you can have determinism.

maxx said:

7) You say that in the second method we have only one possible SYSREF frequency, that is what we have on our board. We have only one SYSREF but it can be configured to have different DAC sampling frequency.

You could have more than one SYRSEF frequency in the second case provided some master is able to generate that frequency, then it gets re-clocked by slave.  In the second case, the slave cannot in most cases generate a SYSREF frequency (because it most likely be at a high frequency like 122.88 MHz).

maxx said:

10) I this moment we have designed the board that can handle basically 4 references clock 10Mhz,16Mhz,19.2Mhz e 30.72MHz configuring the LMK in a dual loop configuration and an external VCO of 122.8Mhz (has the demo board).

There could be some possible challenge for synchronization between boards when using 10 MHz input reference as the N / R will not reduce to have R = 1.

73,
Timothy

CLOCK _28_07.docxHi Timothy, is a busy time also for me, I appreciate a lot your help, thank you for your time.

May you check the schematic in attach at this post, as you can see the clock reference in this new layout comes from a LMK03328 that generates a reference to the LMK04828 (CLKin1) and if , I have understood well, providing the reference clock equal to the SYSREF frequency enable me to have the N/R reduction R equal to 1  enabling the 0-delay and the phased outputs on both the boards.

The CLKin0 is connected to the FPGAs to have a second way to trigger a single synchronous pulse between two boards.

maxx

I think I see how you are using the master's LMK03328 to place a reference through the HMC720LP3E to CLKin1 of both devices.  Provided you use 0-delay feeding back the SYSREF divider, then the SYSREF's will be in phase between the two parts for SYSREF synchronization to downstream devices at your convenience while retaining determinism.

I've not seen any impact to phase noise by 0-delay.

maxx said:

I'm not sure, if in a different way in respect of my schematic, using the CLKin0 insted of clock in 1 will add the possibility to perform better phase sincronization using the direct SYSREF distribution (last entry in the table1 of the PDF), in this configuration I will not able to do a 0-delay with a CLKin0 (if the CLKin0_OUT_MUX is configured as SYSREF input) so with a perfected mached inputs clock ...the two PLLs will run asynchronously.

73,
Timothy

Hi Timothy,

Fine, I've really appreciate your help !
Thanks
Maxx