Hello!
I'm currently trying to use an LMK04803 in Dual-PLL mode to get a fixed phase from input clock to output clocks, with 40MHz on input and 10MHz output.
0-delay (Register 11) is an option, but is no must, so I started with separate PLLs. The important part is that the clocks have a fixed division factor between each other.
When I output the PLL2 DLD, then the LMK signals the digital lock detect as high. But with the PLL1 DLD, the DLD is not asserted (only flickering while programming). So the PLL1 is not locked.
The LMK is connected as follows:
- Input CLK is LVDS with 40MHz
- PLL1 VCO is 100MHz voltage controlled Quartz (CRYSTEK CVHD-950X 100M)
- PLL2 is set to 2GHz
- Output is 2GHz/200 = 10MHz (LVCMOS, normal polarity)
Therefore, I took the Figure in the datasheet (8.2 Functional Block Diagram), to get the needed settings, starting with PLL1:
- CLKin0 Divider = 1 (Reg27)
- Ref Mux (CLKin_Select_MODE) = 0 (Reg13)
- N and R Delay = 0
- R1 divider = 4
- N1 divider = 10
so the PLL1 should use the OSCout0 from the VCXO, so:
- FEEDBACK_MUX = 0, EN_FEEDBACK_MUX=0,
For reference, this are all settings used for the LMK04803 (naming like in the datasheet):
CLKout0_1_DIV: 200
CLKout0_1_HS: 0
Reset: 0
CLKout0_1_DDLY: 5
CLKout0_ADLY_SEL: 0
CLKout1_ADLY_SEL: 0
CLKout0_1_PD: 0
CLKout2_3_DIV: 200
CLKout2_3_HS: 0
Powerdown: 0
CLKout2_3_DDLY: 5
CLKout2_ADLY_SEL: 0
CLKout3_ADLY_SEL: 0
CLKout2_3_PD: 0
CLKout4_5_DIV: 25
CLKout4_5_HS: 0
CLKout4_5_DDLY: 5
CLKout4_ADLY_SEL: 0
CLKout5_ADLY_SEL: 0
CLKout4_5_PD: 0
CLKout6_7_DIV: 25
CLKout6_7_HS: 0
CLKout6_7_DDLY: 5
CLKout6_ADLY_SEL: 0
CLKout7_ADLY_SEL: 0
CLKout6_7_OSCin_Sel: 0
CLKout6_7_PD: 0
CLKout8_9_DIV: 25
CLKout8_9_HS: 0
CLKout8_9_DDLY: 5
CLKout8_ADLY_SEL: 0
CLKout9_ADLY_SEL: 0
CLKout8_9_OSCin_Sel: 0
CLKout8_9_PD: 0
CLKout10_11_DIV: 25
CLKout10_11_HS: 0
CLKout10_11_DDLY: 5
CLKout10_ADLY_SEL: 0
CLKout11_ADLY_SEL: 0
CLKout10_11_PD: 0
CLKout0_1_ADLY: 0
CLKout2_3_ADLY: 0
CLKout0_TYPE: 8
CLKout1_TYPE: 8
CLKout2_TYPE: 1
CLKout3_TYPE: 1
CLKout4_5_ADLY: 0
CLKout6_7_ADLY: 0
CLKout4_TYPE: 1
CLKout5_TYPE: 1
CLKout6_TYPE: 1
CLKout7_TYPE: 1
CLKout8_9_ADLY: 0
CLKout10_11_ADLY: 0
CLKout8_TYPE: 1
CLKout9_TYPE: 1
CLKout10_TYPE: 1
CLKout11_TYPE: 1
Reg9: 1.4317e+09
FEEDBACK_MUX: 0
VCO_DIV: 0
EN_FEEDBACK_MUX: 0
VCO_MUX: 0
OSCout_DIV: 2
PD_OSCin: 0
OSCout0_MUX: 0
OSCout1_MUX: 0
EN_OSCout0: 1
EN_OSCout1: 1
OSCout0_TYPE: 8
OSCout1_LVPECL_AMP: 2
EN_PLL2_XTAL: 0
SYNC_TYPE: 1
SYNC_EN_AUTO: 1
SYNC_POL_INV: 1
SYNC_QUAL: 0
SYNC_MUX: 0
NO_SYNC_CLKout0_1: 0
NO_SYNC_CLKout2_3: 0
NO_SYNC_CLKout4_5: 0
NO_SYNC_CLKout6_7: 0
NO_SYNC_CLKout8_9: 0
NO_SYNC_CLKout10_11: 0
EN_SYNC: 1
MODE: 0
HOLDOVER_MODE: 2
EN_TRACK: 1
Note29: 0
SYNC_PLL1_DLD: 0
SYNC_PLL2_DLD: 0
LD_TYPE: 3
LD_MUX: 1
EN_CLKin0: 1
EN_CLKin1: 1
CLKin_Sel_INV: 0
CLKin_Select_MODE: 0
Status_CLKin0_MUX: 0
DISABLE_DLD1_DET: 0
Status_CLKin0_TYPE: 0
Status_CLKin1_MUX: 0
HOLDOVER_TYPE: 3
HOLDOVER_MUX: 1
EN_VTUNE_RAIL_DET: 0
DAC_LOW_TRIP: 0
DAC_HIGH_TRIP: 0
CLKin0_BUF_TYPE: 0
CLKin1_BUF_TYPE: 0
Status_CLKin1_TYPE: 2
EN_LOS: 1
LOS_TIMEOUT: 0
FORCE_HOLDOVER: 0
HOLDOVER_DLD_CNT: 512
EN_MAN_DAC: 0
MAN_DAC: 512
XTAL_LVL: 3
PLL1_WND_SIZE: 1
PLL1_R_DLY: 0
PLL1_N_DLY: 0
PLL2_R3_LF: 0
PLL2_R4_LF: 0
PLL2_C3_LF: 0
PLL2_C4_LF: 0
PLL1_DLD_CNT: 10000
DAC_CLKDIV: 11
PLL2_CP_TRI: 0
PLL2_DLD_CNT: 8192
PLL2_CP_GAIN: 3
PLL2_CP_POL: 0
EN_PLL2_REF_2X: 0
PLL2_WND_SIZE: 2
PLL1_CP_TRI: 0
PLL1_R: 4
CLKin0_PreR_DIV: 1
CLKin1_PreR_DIV: 0
PLL1_CP_GAIN: 3
CP_POL: 1
PLL1_N: 1
PLL2_R: 1
PLL2_N_CAL: 10
PLL2_FAST_PDF: 0
OSCinFreq: 1
PLL2_N: 10
PLL2_P: 2
uWire_LOCK: 0
READBACK_ADDR: 31
READBACK_LE: 0
Do you see where I made a/the mistake?
BR,
Markus
