Can M-LVDS be used to distribute the PCIe clock to multiple slots, implementing the common clock architecture, and meet jitter requirements for PCIe 3.1?
Thanks,
Brent
This thread has been locked.
If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
Can M-LVDS be used to distribute the PCIe clock to multiple slots, implementing the common clock architecture, and meet jitter requirements for PCIe 3.1?
Thanks,
Brent
Hi Brent,
I believe it can. You might want to re-post here: High Speed Interface Forum