LMK04808BISQE/NOPB_Clock jitter

Auxilian James

Prodigy 220 points

Other Parts Discussed in Thread: LMK04808

We are using ADC16DV160CILQ/NOPB ADC and LMK04808BISQE/NOPB jitter cleaner for
our application

Specification

Input Frequencyof the ADC: 1090MHz

Sampling Clock(PLL output):160MHz/144MHz

Required SNR 60dB

Refernce clock part No: T602.040.0M

Voltage control oscillator part No: CVHD-950X-100.000

By using TI clock design tool, i have enter the Reference clock as a 40Mhz and VCXO as a 100MHz in the customer requirements. Based on that, i select the LMK04808 PLL.

In the simulation page, I have enter the phase noise with respective offset in the phase noise display window for CLKinX. The phase noise and offset value entered as per datasheet and details below mentioned.

Sl.No	Offset (Khz)	Phase Noise (dBc/Hz)
1	0.01	-73
2	0.1	-103
3	1	-134
4	10	-151
5	100	-152
6	1000	-154

In the same window, i have enter the low frequency and high frequency as 0.01KHz and 1000KHz respectively. Based on that value, RMS jitter value is showing as in clock section 2.8Ps. Suppose if i change the low frequency value as 1 KHz instead of 0.01KHz. The RMS jitter value is reduced as a 129fs. In the same way, i have enter the phase noise value for VCXO as per below mentioned

Sl.No	Offset (Khz)	Phase Noise (dBc/Hz)
1	1	-140
2	10	-155
3	100	-164
4	1000	-166

1) So which value i have to consider in the Low frequency and high frequency?

Aperture jitter of the ADC :80 fs (From ADC datasheet)

Based on the RMS jitter 129fs @ clkinput, output RMS jitter @160MHz: 156fs (From Clock design tool simulation)

Total RMS Jitter: 175fs (SQRT(Aperture jitter)^2+(PLL jitter)^2)

Based on the jitter, the SNR value: 58.9dB.(-20log(2*pi()*Fin*total jit))

2) Kindly suggset the selected components( clock and VCXO) are enough to acheive the above mentioned SNR?

over 9 years ago

0 Timothy T over 9 years ago

TI__Mastermind 28550 points

After entering the reference noise and looking at the 10 Hz to 20 MHz integrated noise of the 40 MHz input clock, I also see 2.8 ps. Since the noise is high at the low offset (10 Hz), it will pass directly through to the output unless your PLL1 loop bandwidth is narrow enough to filter that noise. 10 Hz is pretty low, the tool will auto-design a filter as low as 10 Hz. But to filter 10 Hz noise, you would need to design even a lower loop bandwidth. Try typing in manually 0.001 kHz and 50 degree phase margin, then press calculate. You will see some improvement on the output. However you may need to go even lower, 0.0001 (kHz) [will report as 0 Hz as 1 Hz is minimum value the toolprints). And you will see the jitter continue to be attenuated by the VCXO.

Typical procedure is enter new customer phase noise for reference and VCXO. Open LOOPFILTER1 design, auto-recommend, then open LOOPFILTER2 design, auto-recommend. Now your phase noise should be optimized. With the exception that the lowest loop bandwidth the tool recommends is 10 Hz. So you may manually reduce this as described above.

- When doing very narrow PLL1 loop bandwidths, to help reduce the capacitor size, I recommend increasing the PLL1_R value, reducing the PLL1 charge pump value. Note these are defaulted to minimum possible R divider (easy to increase) and maximum charge pump current (best PLL performance). However on the PLL1 narrow loop bandwidth.

Auxilian James said:
1) So which value i have to consider in the Low frequency and high frequency?

As for necessary integration range of output clock, it depends on your application. Less than 10 Hz is considered wander, so below 10 Hz is typically never considered for integration.

Otherwise the minimum offset depends on application. For example, for FFT, the lowest integration range which makes sense is the width of a bin. Refer to the 'Choosing PLL Loop bandwidths' in the E2E files section, at the end there are some times for integration range. Remember, with the clock design tool, what you see in the phase noise window is what you integrate.

Auxilian James said:
2) Kindly suggset the selected components( clock and VCXO) are enough to acheive the above mentioned SNR?

This would depend on the FFT used for the SNR calculation. Bigger bins will obscure some of that noise. On the other hand, I think the VCXO is very good... so it is just a matter of using the very narrow loop bandwidth.

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LMK04808BISQE/NOPB_Clock jitter