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LMK4828 configuration on TSW54J60 EVM board

Other Parts Discussed in Thread: LMK04828, LMK04821

Hello,

I am trying to configure LMK4828 using my own software.

I am trying to use the same configuration as detailed in LMK_Config_Onboard_983p04_MSPS.cfg file. I have pasted the configuration below.

But this configuration file does not seem to include the programming instructions as given section 9.5.1 in the datasheet.

Can you please tell me which steps are missing from the configuration file.

Thanks,

MH

LMK04828
0x00 0x10
0x02 0x00
0x100 0x0C
0x101 0x55
0x103 0x00
0x104 0x20
0x105 0x00
0x106 0xF0
0x107 0x11
0x108 0x63
0x109 0x55
0x10B 0x00
0x10C 0x20
0x10D 0x00
0x10E 0xF0
0x10F 0x06
0x110 0x08
0x111 0x55
0x113 0x00
0x114 0x00
0x115 0x00
0x116 0x79
0x117 0x01
0x118 0x08
0x119 0x55
0x11B 0x00
0x11C 0x00
0x11D 0x00
0x11E 0x79
0x11F 0x01
0x120 0x08
0x121 0x55
0x123 0x00
0x124 0x00
0x125 0x00
0x126 0x79
0x127 0x01
0x128 0x08
0x129 0x55
0x12B 0x00
0x12C 0x00
0x12D 0x00
0x12E 0x79
0x12F 0x01
0x130 0x02
0x131 0x55
0x133 0x00
0x134 0x00
0x135 0x00
0x136 0x79
0x137 0x00
0x138 0x20
0x139 0x00
0x13A 0x03
0x13B 0x00
0x13C 0x00
0x13D 0x08
0x13E 0x03
0x13F 0x00
0x140 0x07
0x141 0x00
0x142 0x00
0x143 0x11
0x144 0x00
0x145 0x00
0x146 0x10
0x147 0x1A
0x148 0x02
0x149 0x42
0x14A 0x33
0x14B 0x16
0x14C 0x00
0x14D 0x00
0x14E 0x00
0x14F 0x7F
0x150 0x03
0x151 0x02
0x152 0x00
0x153 0x00
0x154 0x78
0x155 0x00
0x156 0x7D
0x157 0x00
0x158 0x96
0x159 0x06
0x15A 0x00
0x15B 0xD4
0x15C 0x20
0x15D 0x00
0x15E 0x00
0x15F 0x0B
0x160 0x00
0x161 0x01
0x162 0x44
0x163 0x00
0x164 0x00
0x165 0x0C
0x166 0x00
0x167 0x00
0x168 0x0C
0x169 0x59
0x16A 0x20
0x16B 0x00
0x16C 0x00
0x16D 0x00
0x16E 0x13
0x17C 0x15
0x17D 0x0F
LMK04828
0x139 0x00 //set SYSREF_Mux to "Normal"
0x143 0x11 //set SYNC_MUX to "Pin"
0x140 0x00 //turn on all the blocks, can these just stay on?
0x144 0x74 //enable syncing of all clock outputs
0x143 0x11 //trigger SYNC event using "Pin" mode
0x143 0x31
0x143 0x11
0x144 0xFF //disable syncing of all clock outputs
0x139 0x3  //set SYSREF_MUX to "Continuous"
0x10F 0x66 //enable sysref to adc

  • Hi Channamallesh,

    It seems LMK04828 setting in "LMK_Config_Onboard_983p04_MSPS.cfg" is not optimized. It is better to follow up steps as section 9.5.1 of LMK0482x datasheet, as below.

    "The recommended programming sequence from POR involves:
    1. Program register 0x000 with RESET = 1.

    2. Program registers in numeric order from 0x000 to 0x165. Ensure the following register is programmed as
    follows:
    – 0x145 = 127 (0x7F)
    3. Program register 0x171 to 0xAA and 0x172 to 0x02.
    4. If using LMK04821, program register 0x174.
    5. Program registers 0x17C and 0x17D as required by OPT_REG_1 and OPT_REG_2.
    6. Program registers 0x166 to 0x1FFF.
    When using LMK04821: Program register 0x174, bits 4:0 (VCO1_DIV) with proper value before programming
    PLL2_N register in 0x166, 0x167, and 0x168 for proper total PLL2_N value.
    Program register 0x171, 0x172, 0x17C (OPT_REG_1) and 0x17D (OPT_REG_2) before programming PLL2 in
    registers: 0x166, 0x167, and 0x168 to optimize PLL2_N and VCO1 phase noise performance over temperature."

    I could find some problems in .cfg.

    1, No RESET. It should be started with "0x00 0x90", then "0x00 0x10".

    2, "0x145 0x00" is not a good setting.It should be default 0x7F, Reg 0x171,0x172 also should be default value. It is a good choice to confirm these default value  before we continue to set other registers.

    3, "0x17D 0x0F" is not a good setting for LMK04828, as datasheet shows, we should set "0x17D 0x33". What's more, we should set 0x17C and 0x17D before 0x166, 0x167,0x168.

    For these basic clock setting sequence, you can refer to LMK04828 EVM software "Codeloader", which could export regiser values for your programming.

    For SYSREF generation steps, it is better to follow up "9.3.2.1.1 Setup of SYSREF Example".

    "0x140 0x00 //turn on all the blocks, can these just stay on?" -- You can trun off those unused blocks to save power consumption.

    Best Regards,

    Shawn